ISL22419 Datasheet, PDF (11/13 Pages) Intersil Corporation – Low Noise, Low Power, SPI Bus, 128 Taps, Wiper Only

ISL22419
CS
SCK
SDI
0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0
0 D6 D5 D4 D3 D2 D1 D0
FIGURE 12. THREE BYTE WRITE SEQUENCE
CS
SCK
SDI
SDO
0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0
Don’t Care
0
FIGURE 13. THREE BYTE READ SEQUENCE
D6 D5 D4 D3 D2 D1 D0
Applications Information
Communicating with ISL22419
Communication with ISL22419 proceeds using SPI interface
through the ACR (address 11b), IVR (address 00b) and WR
(address 00b) registers.
The wiper of the potentiometer is controlled by the WR
register. Writes and reads can be made directly to this
register to control and monitor the wiper position without any
non-volatile memory changes. This is done by setting MSB
bit (ACR[7]) at address 11b to 1.
The non-volatile IVR stores the power up value of the wiper.
IVR is accessible when MSB bit (ACR[7]) at address 11b is
set to 0. Writing a new value to the IVR register will set a
new power up position for the wiper. Also, writing to this
register will load the same value into the WR as the IVR.
Reading from the IVR will not change the WR, if its contents
are different.
The typical application diagram is shown in Figure 14. For
proper operation adding 0.1µF decoupling ceramic capacitor
to V_CC is recommended. The capacitor value may vary
based on expected noise frequency of the design.
11
FN6311.1
September 8, 2009