CD4511BMS Datasheet, PDF (11/11 Pages) Intersil Corporation – CMOS BCD-to-7-Segment Latch Decoder Drivers

CD4511BMS
Applications Interfacing with Various Displays (Continued)
MULTIPLEXING SCHEME SHOWING
2 OF 7 SEGMENTS CONNECTED
TRANSISTORS T1 - T4 (2N3053 OR 2N2102)
HAVE IC MAX. RATING > 7 x ISEG
DUTY CYCLE = 25%
ISEG = (IDIODEAVG) x 4
(VOH - VDF-VCE)
R=
ISEG
LT
A
B
C
D
LE
VDD
BL
VSS
VDD
a^R
b
c
d
e
f
g^R
+
-
VOH
ISEG
+
VDF
-
VO1 12 2
Q0 4
1
V02 11
CD4024BMS
2
VO3 9
3
Q1 5
CD4555BMS
1
Q2 6
Q3 7
VSS
+
VCE
T1 _-
VSS
T2
VSS
T3
VSS
T4
VSS
FIGURE 12. MULTIPLEXING WITH COMMON CATHODE 7-SEGMENT LED DISPLAYS (EXAMPLE HEWLET-PACKARD 5082-7404
4 CHARACTER DISPLAY OR 4 DISCRETE MONOSANTO MAN 3 DISPLAYS)
Waveforms
tr
DATA
INPUT
tTHL
OUTPUT
tPHL
tr, tf = 20ns
tf
tTLH
tPLH
90%
50%
10%
VDD
0
90%
50%
10%
VDD
0
20ns
LE
DATA
50%
INPUTS ^10%
20ns
10%
tSU
90%
90%
50%
tHOLD
VDD
0
VDD
50%
0
FOR SETUP
VDD
OUTPUT
20ns
STROBE
90%
50%
tr, tf = 20ns ^10%
tW
FOR HOLD
0
20ns
FIGURE 13. DYNAMIC WAVEFORMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10^-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1179