CD4510BMS Datasheet, PDF (11/11 Pages) Intersil Corporation – CMOS Presettable Up/Down Counters

CD4510BMS, CD4516BMS
UP/DOWN
PRESET
ENABLE
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
PARALLEL CLOCKING
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
*
R CL Q1 Q2 Q3 Q4
CLOCK
RESET
* CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS
IC’S. These negative going glitches do not affect proper CD4029BMS operation. However, if the CARRY OUT signals are used to trigger other edge-
sensitive logic devices, such as FF’S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as
CD4071BMS.
UP/DOWN
PRESET
ENABLE
RIPPLE CLOCKING
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
UP/D PE J1 J2 J3 J4
CI CD4510/16BMS CO
R CL Q1 Q2 Q3 Q4
CLOCK
1/4 CD4071B
RESET
Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the
clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the OR gates
are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded.
FIGURE 15. CASCADING COUNTER PACKAGES
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