CD4510BMS Datasheet, PDF (1/11 Pages) Intersil Corporation – CMOS Presettable Up/Down Counters

Data Sheet
CD4510BMS, CD4516BMS
December 1992
File Number 3338
CMOS Presettable Up/Down Counters
CD4510BMS Presettable BCD Up/Down Counter and the
CD4516BMS Presettable Binary Up/Down counter consist of
four synchronously clocked D-type flip-flops (with a gating
structure to provide T-type flip-flop capability) connected as
counters. These counters can be cleared by a high level on
the RESET line, and can be preset to any binary number
present on the jam inputs by a high level on the PRESET
ENABLE line. The CD4510BMS will count out of non-BCD
counter states in a maximum of two clock pulses in the up
mode, and a maximum of four clock pulses in the down mode.
If the CARRY IN input is held low, the counter advances up or
down on each positive-going clock transition. Synchronous
cascading is accomplished by connecting all clock inputs in
parallel and connecting the CARRY OUT of a less significant
stage to the CARRY IN of a more significant stage.
The CD4510BMS and CD4516BMS can be cascaded in the
ripple mode by connecting the CARRY OUT to the clock of
the next stage. If the UP/DOWN input changes during a ter-
minal count, the CARRY OUT must be gated with the clock,
and the UP/DOWN input must change while the clock is
high. This method provides a clean clock signal to the sub-
sequent counting stage. (See Figures 13, 14.)
These devices are similar to types MC14510 and MC14516.
The CD4510BMS and CD4516BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4510B Only
*H4W †H45
*FBF †H1F
H6W
†CD4516B Only
Pinout
CD4510BMS, CD4516BMS
TOP VIEW
PRESET ENABLE 1
Q4 2
P4 3
P1 4
CARRY IN 5
Q1 6
CARRY OUT 7
VSS 8
16 VDD
15 CLOCK
14 Q3
13 P3
12 P2
11 Q2
10 UP/DOWN
9 RESET
Features
• High Voltage Types (20V Rating)
• CD4510BMS - BCD Type
• CD4516BMS - Binary Type
• Medium Speed Operation
- fCL = 8MHz Typ. at 10V
• Synchronous Internal Carry Propagation
• Reset and Preset Capability
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Up/Down Difference Counting
• Multistage Synchronous Counting
• Multistage Ripple Counting
• Synchronous Frequency Dividers
Functional Diagram
PRESET ENABLE
1
4
P1
12
P2
13
P3
3
P4
6
Q1
11
Q2
14
Q3
2
Q4
15
CLOCK
10
UP/DOWN
5
CARRY IN
RESET
7
CARRY OUT
9
VDD = 16
VSS = 8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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