ISL6560 Datasheet, PDF (10/14 Pages) Intersil Corporation – Microprocessor CORE Voltage Regulator Two-Phase Buck PWM Controller

ISL6560
To calculate the dissipation in the 5mΩ resistor, we used
only half of the ripple current, 4A, to give a nominal
dissipation of:
I_RMS = Ip
D = Ip
1_----._--8_---V_---
12 V
∴Power = Ip² × D × R_SENSE = 30.4² × 0.15^· × 5mΩ
Power = 0.69W per channel or 1.38W for both channels
Where I_P is the peak current and D is the duty cycle. Two
10mΩ, 1W resistors in parallel were selected.
R_L Selection
As discussed in the section under Droop Voltage and shown
in Figure 1, resistor R_L establishes the gain of the
transconductance error amplifier. It is this resistor that sets
the droop voltage or regulation. Like any feedback system,
the higher the gain the better the regulation. The value of this
resistor may be determined from the following equation:
R_L = _g---ⁿ-_m---ⁱ---^×-_×----^R-_R---^S-_O---^E--_U--^N--_T--^S---_×-^E---₂-- = ₂----_.--₂---_m----¹--_S-²---^.-_×-⁵----₁-^×--_.--₆-⁵--₃--^m--_m---^Ω---_Ω------_×-----₂- = 8.7kΩ
∴gmgmAmAmplpiflifeierrGGaainin==gm × RL = 2.2mS × 8.7k = 19.1
The ni term is the ratio of the V_COMP to the current
comparator threshold voltage; see Figure 2. R_L is made up
of two resistors that form a voltage divider from the internal
3V reference supply.
As described earlier in the Circuit Description section, the
output voltage of the gm amplifier establishes the threshold
voltage of the current comparator. At approximately 1V, the
current comparator threshold voltage is near zero. With no
current demands, the regulator output voltage would be the
same as the programmed DAC voltage. However, an 8A
ripple current was selected for this design. This results in the
output of the gm amplifier moving upwards to supply the
ripple current. The voltage at the COMP pin, V_SET, will be:
V_SET
=
1V + ^I--^R-----^I-^P----^P----^L----^E-----^×----^R-----^S----^E----^N----^S----^E-----^×-----ⁿ---ⁱ
2
= 1V + ⁸----^A------^×-----⁵---^m------^Ω------^×-----¹---²----^.-⁵-- = 1V + 250mV = 1.25V
2
The voltage divider establishes the reference voltage for
V_COMP that was set to 1.2V for this design, so the error
amplifier must drive the COMP pin 50mV more positive to
bring it to 1.25V from the 1.2V originally set. This additional
50mV output will result in an input voltage to the error
amplifier of: 50mv / 19.1 = 2.62mV below the programmed
DAC voltage of 1.8V. Neglected, is a negative term
associated with the 60ns delay of the current comparator.
This delay will cause the current ramp to be slightly greater
than predicted by the equation. This means that the initial
setting should be slightly reduced to account for the increase
in current.
Once the value for R_L is set, only the values of the resistors
that make up the voltage divider must be determined. Figure
8 shows the equations to determine the resistor network that
makes up R_L.
V_{REF = 3V}
R_U || R_B = R_L
R_U
V_SET
=
1V + ^I--^R-----^I-^P----^P----^L----^E-----^×----^R-----^S----^E----^N----^S----^E-----^×-----ⁿ---ⁱ
2
To COMP pin,
this voltage is V_SET
R_U
=
V_{-----R----E----F-}
V_SET
×
R_L
R_B
R_U
=
-----³----^V------ × 8.7k
1.25 V
=
20.9 k
R_B
=
-----------^V-----^S---^E----^T-------------
V_REF – V_SET
×
R_U
R_B =
-------¹----^.-²----⁵----^V--------- × 20.9k
3V – 1.25V
=
14.9 k
FIGURE 8. EQUATIONS TO DETERMINE R_L DIVIDER
C_C and R_C Selection
Optimum transient response depends upon the selection of
the compensation capacitor network placed across the
output of the transconductance error amplifier.
To a first order, the selection of the capacitor, C_C, placed
across the error amplifier may be determined by making the
product of the regulator output resistance and output
capacitors equal to the product of the R_L and C_C. This yields
the equation for the compensation capacitor:
C_C
=
R_{-----O-----U----T----}×_-----C_{-----O----U-----T-}
R_L
=
1_----._--6_---3_----m_-----Ω_------×_-----9_----m_-----F_--
8.7 k
=
1.68 n F
A 1nF capacitor was selected from transient testing. To
prevent excessive phase shift due to the compensation
capacitor, it is usually necessary to place a resistor inseries
with the capacitor to prevent excessive phase shift beyond
the frequency of interest. This is pole cancellation and the
resistor is approximately 0.5 x R_L. Figure 9 shows this
network and the equivalent circuit is approximately 0.5 x R_L.
Many variables have been used in the selection of the
various gain and filter networks to this point. A broad range
of component tolerances range from ±1% to ±20% have
been used in the design. Therefore, it is important to
evaluate the entire system with dynamic pulse load testing.
This will verify optimum transient response and also indicate
poor response in terms of excessive overshoot, ringing or
oscillation if the compensation network is not optimum.
V_{REF = 3V}
AC Equivalent
RU
C_C
C_C
To COMP pin
R_B
R_C
R_L
R_C
R_C = 0.5 x R_L
FIGURE 9. COMPENSATION CIRCUIT
10
FN9011.3