ISL59420_14 Datasheet, PDF (10/13 Pages) Intersil Corporation – 400MHz Multiplexing Amplifier

ISL59420
Application Information
General
The ISL59420 is a 2:1 mux that is ideal as a matrix element in
high performance switchers and routers. The ISL59420 is
optimized to drive 5pF in parallel with a 500Ω load. The
capacitance can be split between the PCB capacitance and an
external load capacitance. Its low input capacitance and high
input resistance provide excellent 50Ω or 75Ω terminations.
Parasitic Effects on Frequency
Performance
Capacitance at the Inverting Input
The AC performance of current-feedback amplifiers in the
non-inverting gain configuration is strongly affected by stray
capacitance at the inverting input. Stray capacitance from the
inverting input pin to the output (C_F), and to ground (C_G),
increase gain peaking and bandwidth. Large values of either
capacitance can cause oscillation. The ISL59420 has been
optimized for a 0.4pF to 0.7pF capacitance (C_G). Capacitance
(C_F) to the output should be minimized. To achieve optimum
performance the feedback network resistor(s) must be placed
as close to the device as possible. Trace lengths greater than
1/4 inch combined with resistor pad capacitance can result in
inverting input to ground capacitance approaching 1pF.
Inverting input and output traces should not run parallel to
each other. Small size surface mount resistors (604 or
smaller) are recommended.
Capacitance at the Output
The output amplifier is optimized for capacitance to ground
(C_L) directly on the output pin. Increased capacitance causes
higher peaking with an increase in bandwidth. The optimum
range for most applications is ~1.0pF to ~6pF. The optimum
value can be achieved through a combination of PC board
trace capacitance (C_T) and an external capacitor (C_OUT). A
good method to maintain control over the output pin
capacitance is to minimize the trace length (C_T) to the next
component, and include a discrete surface mount capacitor
(C_OUT) directly at the output pin.
Feedback Resistor Values
The AC performance of the output amplifier is optimized with
the feedback resistor network (R_F, R_G) values recommended in
the application circuits. The amplifier bandwidth and gain
peaking are directly affected by the value(s) of the feedback
resistor(s) in unity gain and gain >1 configurations. Transient
response performance can be tailored simply by changing
these resistor values. Generally, lower values of R_F and R_G
increase bandwidth and gain peaking. This has the effect of
decreasing rise/fall times and increasing overshoot.
Ground Connections
For the best isolation and crosstalk rejection, the GND pin and
NIC pins must connect to the GND plane.
Control Signals
S0, ENABLE, HIZ - These pins are TTL/CMOS compatible
control inputs. The S0 pin selects which one of the inputs
connect to the output. The ENABLE, HIZ pins are used to
disable the part to save power and three-state the output
amplifiers, respectively. For control signal rise and fall times
less than 10ns the use of termination resistors close to the
part will minimize transients coupled to the output.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins
the V+ and V- supplies. In addition, a dV/dT- triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 section of the Pin Description
table. The dV/dT triggered clamp imposes a maximum supply
turn-on slew rate of 1V/µs. Damaging currents can flow for
power supply rates-of-rise in excess of 1V/µs, such as during
hot plugging. Under these conditions, additional methods
should be employed to ensure the rate of rise is not exceeded.
Consideration must be given to the order in which power is
applied to the V+ and V- pins, as well as analog and logic input
pins. Schottky diodes (Motorola MBR0550T or equivalent)
connected from V+ to ground and V- to ground (Figure 24) will
shunt damaging currents away from the internal V+ and V- ESD
diodes in the event that the V+ supply is applied to the device
before the V- supply.
If positive voltages are applied to the logic or analog video
input pins before V+ is applied, current will flow through the
internal ESD diodes to the V+ pin. The presence of large
decoupling capacitors and the loading effect of other circuits
connected to V+, can result in damaging currents through the
ESD diodes and other active circuits within the device.
Therefore, adequate current limiting on the digital and analog
inputs is needed to prevent damage during the time the
voltages on these inputs are more positive than V+.
HIZ State
An internal pull-down resistor connected to the HIZ pin ensures
the device will be active with no connection to the HIZ pin. The
HIZ state is established within approximately 25ns (Figure 19)
by placing a logic high (>2V) on the HIZ pin. If the HIZ state is
selected, the output is a high impedance 1.4MΩ. Use this state
to control the logic when more than one mux shares a
common output.
In the HIZ state the output is three-stated, and maintains its high
Z even in the presence of high slew rates. The supply current
during this state is basically the same as the active state.
ENABLE & Power Down States
The enable pin is active low. An internal pull-down resistor ensures
the device will be active with no connection to the ENABLE pin.
The Power Down state is established when a logic high (>2V) is
placed on the ENABLE pin. In the Power Down state, the output
has no leakage but has a large capacitance (on the order of
15pF), and is capable of being back-driven. Under this condition,
large incoming slew rates can cause fault currents of tens of mA.
Do not use this state as a high Z state for applications driving
more than one mux on a common output.
10
FN7459.2
July 3, 2012