HCTS646MS Datasheet, PDF (1/11 Pages) Intersil Corporation – Radiation Hardened Octal Bus Transceiver/Register, Three-State

HCTS646MS
August 1995
Radiation Hardened
Octal Bus Transceiver/Register, Three-State
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Rate 2 x 10^-9 Errors/Bit Day
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2
• Input Current Levels Ii ≤ 5µA at VOL, VOH
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
CAB 1
SAB 2
DIR 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 VCC
23 CBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
Description
The Intersil HCTS646MS is a Radiation Hardened Three-
State Octal Bus Tranceiver/Register with Non-Inverting
outputs. This device is a bus transceiver with D-type flip-flops
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
which act as internal storage registers. Data on the A bus or
the B bus can be clocked into the registers on a High-to-Low ^CAB
1
24
VCC
transition of either CAB ro CBA clock inputs. Output enable ^SAB
2
23
CBA
(OE) and Direction (DIR) inputs control the transceiver func- ^DIR
3
22
SBA
tions. Data present at the high impedance output can be
A0
4
21
OE
stored in either register or both but only one of the two buses
A1
can be enabled as outputs at any one time. The select con-
A2
A3
5
20
6
19
7
18
B0
B1
B2
trols (SAB and SBA) can multiplex stored and transparent
A4
8
17
B3
(real time) data. The direction control determines which data _A5
9
16
B4
bus will receive data when the OE pin is LOW. In the high _A6
10
15
B5
impedance mode (OE high), A data can be stored in one reg- A7
11
14
B6
ister and B data in the other register. Data at the A or B termi- GND
12
13
B7
nals can be clocked into the storage flip-flops at any time.
The HCTS646MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS646MS is supplied in a 24 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCTS646DMSR
HCTS646KMSR
HCTS646D/Sample
HCTS646K/Sample
HCTS646HMSR
TEMPERATURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
+25^oC
+25^oC
+25^oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
706
PACKAGE
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead SBDIP
24 Lead Ceramic Flatpack
Die
Spec Number 518628
File Number 3074.1