HCTS160MS Datasheet, PDF (1/9 Pages) Intersil Corporation – Radiation Hardened Synchronous Counter

HCTS160MS
September 1995
Radiation Hardened
Synchronous Counter
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset: >10¹⁰ RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
-Standard Outputs 10 LSTTL Loads
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
-VIL = 0.8V Max
-VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA @ VOL, VOH
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
MR 1
CP 2
P0 3
P1 4
P2 5
P3 6
PE 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
9 SPE
Description
16 LEAD CERAMIC METAL SEAL
The Intersil HCTS160MS is a Radiation Hardened high speed
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
presettable BCD decade synchronous counter that features an
TOP VIEW
asynchronous reset and look-ahead carry logic. Counting and
parallel presetting are accomplished synchronously with the low- ^MR
1
16
VCC
to-high transition of the clock. A low level on the synchronous ^CP
2
15
TC
parallel enable input, SPE, disables counting and allows data at P0
3
14
Q0
the preset inputs, P0 - P3, to be loaded into the counter. The _P1
4
13
Q1
counter is reset by a low on the master reset input, MR. Two count
P2
5
12
Q2
enables, PE and TE are provided for n-bit cascading. TE also
P3
6
11
Q3
controls the terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used to ^PE
7
10
TE
enable the next cascaded stage to count.
GND
8
9
SPE
The HCTS160MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS160MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCTS160DMSR
HCTS160KMSR
HCTS160D/Sample
HCTS160K/Sample
HCTS160HMSR
TEMPERATURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
+25^oC
+25^oC
+25^oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
560
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Spec Number 518611
File Number 2484.2