HCS10MS Datasheet, PDF (1/8 Pages) Intersil Corporation – Radiation Hardened Triple 3-Input NAND Gate

HCS10MS
September 1995
Radiation Hardened
Triple 3-Input NAND Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (SI)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10^-9 Errors/Gate Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-183S CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCS10MS is a Radiation Hardened Triple 3-Input
NAND Gate. A high on all inputs forces the output to a Low state.
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-183S CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
A2
B2
C2
Y2
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
C1
Y1
C3
B3
A3
Y3
The HCS10MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS10MS is supplied in a 14 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCS05DMSR -55^oC to +125^oC Intersil Class 14 Lead SBDIP
S Equivalent
HCS05KMSR -55^oC to +125^oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCS05D/
Sample
+25^oC
Sample
14 Lead SBDIP
HCS05K/
Sample
+25^oC
Sample
14 Lead Ceramic
Flatpack
HCS05HMSR
+25^oC
Die
Die
Functional Diagram
An
(1, 3, 9)
Bn
(2, 4, 10)
Cn
(5, 11, 13)
Yn
(12, 6, 8)
TRUTH TABLE
INPUTS
OUTPUTS
An
Bn
Cn
Yn
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
L
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number 518747
File Number 2435.2