CD4093BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Quad 2-Input NAND Schmitt Triggers

CD4093BMS
December 1992
CMOS Quad 2-Input
NAND Schmitt Triggers
Features
Pinout
• High Voltage Types (20V Rating)
• Schmitt Trigger Action on Each Input With No External
Components
• Hysteresis Voltage Typically 0.9V at VDD = 5V and
2.3V at VDD = 10V
• Noise Immunity Greater than 50%
• No Limit on Input Rise and Fall Times
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range, 100nA at 18V and +25^oC
CD4093BMSMS
TOP VIEW
A1
B2
J=A·B 3
K=C·D 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G · H
10 L = E · F
9F
8E
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of _{Functional Diagram}
‘B’ Series CMOS Devices”
Applications
• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
• Astable Multivibrators
• NAND Logic
Description
CD4093BMS consists of four Schmitt trigger circuits. Each
circuit functions as a two input NAND gate with Schmitt trig-
ger action on both inputs. The gate switches at different
points for positive and negative going signals. The difference
between the positive voltage (VP) and the negative voltage
(VN) is defined as hysteresis voltage (VH) (see Figure 1).
The CD4093BMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP H4H
Frit Seal DIP
H1B
Ceramic Flatpack H3W
A1
B2
J3
K4
C5
D6
VSS ⁷
J=A·B
14 ^VDD
13 ^H
K=C·D
L=E·F
12 G
11 M
10 L
9F
M=G·H
8E
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1074
File Number 3330