CD4089BMS Datasheet, PDF (1/10 Pages) Intersil Corporation – CMOS Binary Rate Multiplier

CD4089BMS
December 1992
CMOS Binary Rate Multiplier
Features
• High Voltage Type (20V Rating)
• Cascadable in Multiples of 4 Bits
• Set to “15” Input and “15” Detect Output
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
conjunction with an up/down counter and control logic used
to perform arithmetic operations (adds, subtract, divide, raise
to a power), solve algebraic and differential equations,
generate natural logarithms and trigometric functions, A/D
and D/A conversions, and frequency division.
For words of more than 4 bits, CD4089BMS devices may be
cascaded in two different modes: an Add mode and a Multi-
ply mode (see Figures 3 and 4). In the Add mode some of
the gaps left by the more significant unit at the count of 15
are filled in by the less significant units. For example, when
two units are cascaded in the Add mode and programmed to
11 and 13, respectively, the more significant unit will have 11
output pulses for every 16 input pulses and the other unit will
have 13 output pulses for every 256 input pulses for a total of
11
13
189
+
=
16 256 256
In the Multiply mode the fraction programmed into the first
rate multiplier is multiplied by the fraction programmed into
the second multiplier. Thus the output rate will be
11
13
143
16 ^x 16 ⁼ 256
• Numerical Control
• Instrumentation
• Digital Filtering
• Frequency Synthesis
Description
CD4089BMS is a low power 4 bit digital rate multiplier that
provides an output pulse rate that is the clock-input-pulse
rate multiplied by ¹/₁₆ times the binary input. For example,
when the binary input number is 13, there will be 13 output
pulses for every 16 input pulses. This device may be used in
The CD4089BMS has an internal synchronous 4 bit counter
which, together with one of the four binary input bits, pro-
duces pulse trains as shown in Figure 6.
If more than one binary input bit is high, the resulting pulse
train is a combination of the separate pulse trains as shown
in Figure 6.
The CD4089BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H2R
H6P
Pinout
CD4089BMS
TOP VIEW
“15” OUT 1
C2
D3
SET TO “15” 4
OUT 5
OUT 6
INHIBIT OUT (CARRY) 7
VSS 8
16 VDD
15 B
14 A
13 CLEAR
12 CASCADE
11 INHIBIT IN (CARRY)
10 STROBE
9 CLOCK
Functional Diagram
CLOCK
9
INHIBIT
(CARRY) IN
11
SET TO
“15”
4
4 BIT
BINARY
COUNTER
CLEAR
13
7
VDD = 16
VSS = 8
BINARY RATE
SELECT INPUTS
A B CD
14 15 2 3
STROBE
10
CASCADE
12
RATE
SELECT
LOGIC
OUT
6
OUT
5
“15” OUT
1
RATE
OUTPUTS
INHIBIT (CARRY) OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1064
File Number 3329