CD4085BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

CD4085BMS
December 1992
CMOS Dual 2 Wide 2 Input
AND-OR-INVERT Gate
Features
Pinout
• High Voltage Type (20V Rating)
• Medium Speed Operation
- tPHL = 90ns
- tPLH = 125ns (Typ.) at 10V
• Individual Inhibit Controls
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4085BMS contains a pair of AND-OR-INVERT gates, each
consisting of two 2 input AND gates driving a 3 input NOR gate.
Individual inhibit controls are provided for both A-O-I gates..
The CD4085BMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4H
H1B
H5W
CD4085BMS
TOP VIEW
A1 1
B1 2
E1 = INHI + A1B1 + C1D1 3
E2 = INH2 + A2B2 + C2D2 4
A2 5
B2 6
VSS 7
Functional Diagram
10
INHIBIT 1
1
A1
2
B1
12
C1
13
D1
11
INHIBIT 2
5
A2
6
B2
8
C2
9
D2
14 VDD
13 D1
12 C1
11 INHIBIT 2
10 INHIBIT 1
9 D2
8 C2
3
E1
4
E2
E = INHIBIT + AB + CD
LOGIC 1 = HIGH
LOGIC 0 = LOW
VDD = 14
VSS = 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1046
File Number 3327