CD4041BMS Datasheet, PDF (1/7 Pages) Intersil Corporation – CMOS Quad True/Complement Buffer

Data Sheet
CD4041UBMS
December 1992
File Number 3309
CMOS Quad True/Complement Buffer
CD4041UBMS types are quad true/complement buffers con-
sisting of n- and p- channel units having low channel resis-
tance and high current (sourcing and sinking) capability. The
CD4041UBMS is intended for use as a buffer, line driver, or
CMOS-to-TTL driver. It can be used as an ultra-low power
resistor-network driver for A/D and D/A conversion, as a
transmission-line driver, and in other applications where high
noise immunity and low power dissipation are primary
design requirements.
The CD4041UBMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
Pinout
CD4041UBMS
TOP VIEW
E=A 1
F=A 2
A3
G=B 4
H=B 5
B6
VSS 7
14 VDD
13 D
12 N = D
11 M = D
10 C
9 L=C
8 K=C
Features
• High Voltage Type (20V Rating)
• Balanced Sink and Source Current; Approximately 4
Times Standard “B” Drive
• Equalized Delay to True and Complement Outputs
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25^oC
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specificationsfor Description of
‘B’ Series CMOS Devices”
Applications
• High Current Source/Sink Driver
• CMOS-to-DTL/TTL Converter Buffer
• Display Driver
• MOS Clock Driver
• Resistor Network Driver (Ladder or Weighted R)
• Buffer
• Transmission Line Driver
Functional Diagram
3
A
6
B
10
C
13
D
VSS = 7
VDD = 14
1
E
E=A
2
F
F=A
4
G
G=B
5
H
H=B
8
K
K=C
9
L
L=C
11
M
M=D
12
N
N=D
VDD
VDD VDD
INPUT*
TRUE
OUTPUT
VSS
*ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
VSS
VSS
P
N
VSS
VDD
COMPLEMENT
OUTPUT
VDD
VSS
FIGURE 1. SCHEMATIC DIAGRAM 1 OF 4 BUFFERS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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