CD40106BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Hex Schmitt Triggers

CD40106BMS
December 1992
CMOS Hex Schmitt Triggers
Features
Pinout
• High Voltage Type (20V Rating)
• Schmitt Trigger Action with No External Components
CD40106BMS
TOP VIEW
• Hysteresis Voltage (Typ.)
- 0.9V at VDD = 5V
- 2.3V at VDD = 10V
- 3.5V at VDD = 15V
• Noise Immunity Greater than 50%
• No Limit on Input Rise and Fall Times
• Low VDD to VSS Current During Slow Input Ramp
• 100% Tested for Quiescent Current at 20V
A1
G=A 2
B3
H=B 4
C5
I=C 6
VSS 7
14 VDD
13 F
12 L = F
11 E
10 K = E
9D
8 J=D
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
Functional Diagram
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
1
A
3
B
2
G=A
4
H=B
Applications
5
C
6
I=C
• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
• Astable Multivibrators
9
D
11
E
8
J=D
10
K=E
Description
13
F
12
L=F
CD40106BMS consists of six Schmitt trigger circuits. Each
circuit functions as an inverter with Schmitt trigger action on
the input. The trigger switches at different points for positive
and negative going signals. The difference between the
positive going voltage (VP) and the negative going voltage
(VN) is defined as hysteresis voltage (VH) (see Figure 17).
The CD40106BMS is supplied in these 14 lead outline
packages:
Logic Diagram
A^*
1 (3, 5, 9, 11, 13)
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
* ^{ALL INPUTS ARE PROTECTED}
BY CMOS PROTECTION
NETWORK
*_G
2 (4, 6, 8, 10, 12)
VDD
VSS
FIGURE 1. 1 OF 6 SCHMITT TRIGGERS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1327
File Number 3354