290676-002 Datasheet, PDF (85/119 Pages) Intel Corporation – Intel 810E Chipset: 82810E Graphics and Memory Controller Hub (GMCH)

Intel^® 82810E (GMCH)
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4.3.3. DRAM Array Connectivity
Figure 6. DRAM Array Sockets (2 DIMM Sockets)
SCS[3:2]#
SCS[1:0]#
SCKE0
SCKE1
SRAS#
SCAS#
SWE#
SBS[1:0]
SMAA[11:8,3:0]
SMAA[7:4]
SMAB[7:4]#
SDQM[7:0]
SMD[63:0]
DIMM_CLK[3:0]
DIMM_CLK[7:4]
SMB_CLK
SMB_DATA
Note:
- Min (16Mbit) 8 MB
- Max (64Mbit) 256 MB
- Max (128Mbit) 512 MB
mem_dimm
4.3.4. SDRAMT Register Programming
Several DRAM timing parameters are programmable in the GMCH configuration registers. Table 14
summarizes the programmable parameters.
Table 14. Programmable SDRAM Timing Parameters
Parameter
DRAMT Bit
Values (SCLKs)
RAS# Precharge (SRP)
RAS# to CAS# Delay (SRCD)
CAS# Latency (CL)
DRAM Cycle Time (DCT)
0
2,3
1
2,3
2
2,3
4
Tras = 5,6
Trc = 7,8
These parameters are controlled via the DRAMT register. In order to support different device speed
grades, CAS# Latency, RAS# to CAS# Delay, and RAS# Precharge are all programmable as either two
or three SCLKs. To provide flexibility, these are each controlled by separate register bits. That is, the
GMCH can support any combination of CAS# Latency, RAS# to CAS# Delay and RAS# Precharge.
Datasheet
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