290676-002 Datasheet, PDF (3/119 Pages) Intel Corporation – Intel 810E Chipset: 82810E Graphics and Memory Controller Hub (GMCH)

Intel^® 82810E (GMCH)
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Contents
1.
Overview .....................................................................................................................................11
1.1. The Intel^® 810E Chipset System ....................................................................................11
1.2. GMCH Overview ............................................................................................................13
1.3. Host Interface.................................................................................................................14
1.4. System Memory Interface ..............................................................................................14
1.5. Display Cache Interface .................................................................................................14
1.6. Hub Interface..................................................................................................................14
1.7. GMCH Graphics Support ...............................................................................................15
1.7.1. Display, Digital Video Out, and LCD/Flat Panel ...........................................15
1.8. System Clocking ............................................................................................................16
1.9. References.....................................................................................................................16
2.
Signal Description.......................................................................................................................17
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
Host Interface Signals ....................................................................................................18
System Memory Interface Signals .................................................................................19
Display Cache Interface Signals ....................................................................................20
Hub Interface Signals.....................................................................................................20
Display Interface Signals................................................................................................21
Digital Video Output Signals/TV-Out Pins......................................................................22
Power Signals ................................................................................................................23
Clock Signals .................................................................................................................23
Miscellaneous Interface Signals.....................................................................................24
Power-Up/Reset Strap Options......................................................................................24
3.
Configuration Registers ..............................................................................................................25
3.1. Register Nomenclature and Access Attributes ..............................................................25
3.2. PCI Configuration Space Access ...................................................................................26
3.2.1. PCI Bus Configuration Mechanism ..............................................................26
3.2.2. Logical PCI Bus #0 Configuration Mechanism.............................................27
3.2.3. Primary PCI (PCI0) and Downstream Configuration Mechanism ................27
3.2.4. Internal Graphics Device Configuration Mechanism....................................27
3.2.5. GMCH Register Introduction........................................................................27
3.3. I/O Mapped Registers ....................................................................................................28
3.3.1. CONFIG_ADDRESSConfiguration Address Register ..............................28
3.3.2. CONFIG_DATAConfiguration Data Register ...........................................29
3.4. Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0)....................30
3.4.1. VIDVendor Identification Register (Device 0)...........................................31
3.4.2. DIDDevice Identification Register (Device 0) ...........................................31
3.4.3. PCICMDPCI Command Register (Device 0)............................................32
3.4.4. PCISTSPCI Status Register (Device 0) ...................................................33
3.4.5. RIDRevision Identification Register (Device 0) ........................................34
3.4.6. SUBCSub-Class Code Register (Device 0) .............................................34
3.4.7. BCCBase Class Code Register (Device 0) ..............................................34
3.4.8. MLTMaster Latency Timer Register (Device 0) .......................................35
3.4.9. HDRHeader Type Register (Device 0) .....................................................35
3.4.10. SVIDSubsystem Vendor Identification Register (Device 0)......................35
3.4.11. SIDSubsystem Identification Register (Device 0).....................................36
Datasheet
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