290676-002 Datasheet, PDF (17/119 Pages) Intel Corporation – Intel 810E Chipset: 82810E Graphics and Memory Controller Hub (GMCH)

Intel^® 82810E (GMCH)
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2. Signal Description
This section provides a detailed description of the GMCH signals. The signals are arranged in functional
groups according to their associated interface. The states of all of the signals during reset are provided in
the System Reset section.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when
at the high voltage level.
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/OD
Input / Open Drain Output pin. This pin requires a pullup to the VCC of the processor
core
I/O
Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal:
AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details
CMOS The CMOS buffers are Low Voltage TTL compatible signals. These are 3.3V only.
LVTTL Low Voltage TTL compatible signals. There are 3.3V only.
1.8V
1.8V signals for the digital video interface
Analog Analog CRT Signals
Note that the processor address and data bus signals (Host Interface) are logically inverted signals (i.e.,
the actual values are inverted of what appears on the processor bus). This must be taken into account and
the addresses and data bus signals must be inverted inside the GMCH. All processor control signals
follow normal convention. A 0 indicates an active level (low voltage) if the signal is followed by #
symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix.
Datasheet
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