21285 Datasheet, PDF (85/159 Pages) Intel Corporation – Microprocessor

Functional Units
6.5.4
6.5.5
6.5.6
Baud Rate Generation
The baud rate is derived by dividing down the 21285 clock (fclk_in). The signal fclk_in is divided
by four and used as the reference clock. That clock is first divided by a programmable number
between 1 and 1024, and then by a fixed value of 16. The receive/transmit baud clock is
synchronized with the data stream each time a transition is detected on the receive data line.
Receive data is sampled halfway through each bit period by counting 8 of the 16 clocks that are
produced before the fixed divide by 16 takes place.
Receive Operation
The UART receives incoming data using a serial shifter; latches the frame; and strips it of its start,
parity, and stop bits; and then places the data within the receive FIFO. If parity is enabled, the
number of data bits (that are one) are counted, as data is extracted from each frame. Parity is then
checked by comparing this value to the stripped parity bit. Either odd or even parity is used as
specified by the programmer. If a parity error is detected, the parity error bit is set in the FIFO
entry corresponding to the data. If a logic zero is detected by the receive logic where a stop bit (or
bits) was expected, the framing error bit is set in the FIFO entry corresponding to the data. When
the FIFO fills more than halfway, an interrupt is signaled. If the data is not removed soon enough,
and the FIFO is completely filled, an overrun bit is set in RXSTAT if the receive logic attempts to
place additional data within the FIFO. If the UART is disabled and a one-to-zero transition is
detected (a start bit), the receiver status interrupt is signaled. (This dual-purpose interrupt is also
signaled if the UART is enabled, the receive FIFO contains valid data, and a 32-bit period has
elapsed without the reception of data on rx.)
Transmit Operation
The UART transmit logic operates at the same time as the receive logic (full-duplex). Data is taken
from the transmit FIFO; start, parity, and stop bits are added to generate a frame; and the value is
loaded into a serial shift register. The contents are shifted out onto the tx pin and clocked by the
baud clock. When the transmit FIFO is emptied more than halfway, an interrupt is signaled. If new
data is not supplied soon enough, and the FIFO is completely emptied, the transmit line is forced
high (one) to indicate the idle state.
21285 Core Logic for SA-110 Datasheet
6-13