21285 Datasheet, PDF (123/159 Pages) Intel Corporation – Microprocessor

Registers
7.3.13 SDRAM Address and Size Registers—Offsets 110h to 11Ch
The SDRAM address and size registers consist of four registers controlling array 0 through array 3.
These four registers define each of the four SDRAM arrays’ start address, size, and address
multiplexing. Software must ensure that the arrays of SDRAM are mapped so there is no overlap
of addresses. The arrays do not need to all be the same size, however, the start address of each
array must be naturally aligned to the size of the array. The arrays do not need to form a contiguous
address space, but to do so with different size arrays, place the largest array at the lowest address,
next largest array above, and so on.
Note: The 21285 does not detect memory accesses to nonexistent memory locations. The SDRAM
sequencer may possibly toggle address and command pins, return unpredictable read data on reads,
and discard data on writes.
Dword Bit
2:0
3
6:4
19:7
27:20
31:28
Name
Array size
—
Address
multiplex
—
Array base
—
R/W Description
R/W Indicates the size of the SDRAM array. This field is decoded to
form a mask that is used in comparing the memory address to the
array base field when determining if the address is in this array.
• 000=0 (array disabled)
• 001=1MB (compare bits [27:20])
• 010=2MB (compare bits [27:21])
• 011=4MB (compare bits [27:22])
• 100=8MB (compare bits [27:23])
• 101=16MB (compare bits [27:24])
• 110=32MB (compare bits [27:25])
• 111=64MB (compare bits [27:26])
Reset value: Undefined.
R
Read only as 0.
R/W Controls the row and column multiplexer and implicitly defines the
number of banks in the SDRAM array according to Table 4-2.
Reset value: Undefined.
R
Read only as 0.
R/W Indicates the base address of the array. This value is compared to
address bits [27:20], masked by the decoded array size field, to
determine which array of SDRAMs the address is located in.
Reset value: Undefined.
R
Read only as 0.
21285 Core Logic for SA-110 Datasheet
7-33