21285 Datasheet, PDF (115/159 Pages) Intel Corporation – Microprocessor

Registers
7.3.6
Dword Bit
7
Name
Channel chain done
9:8
Channel interburst
delay prescale
14:10
15
—
PCI read length
18:16
SDRAM read length
31:19
—
R/W
W1C
Description
(Sheet 2 of 2)
Indicates that a chain has completed either normally or
due to an error condition. When this bit is a 1, it can
interrupt the
SA-110 if enabled in the FIQ/IRQEnable register.
Reset value: 0.
R/W
Indicates the prescale value for the counter that
determines the number of SA-110 cycles that the channel
waits before attempting another PCI burst. The number
of counts of the prescaled value is read in the descriptor.
• 00=4
• 01=8
• 10=16
• 11=32
Reset value: Undefined.
R
Read only as 0.
R/W
This field defines the number of Dwords that the 21285
attempts to read per burst from the PCI during PCI-to-
SDRAM transfers (during the beginning or end of a
transfer the number may be less).
• 0=8 Dwords
• 1=16 Dwords
Reset value: Undefined.
R/W
This field defines the number of Dwords read from
SDRAM per burst for SDRAM-to-PCI transfers (during the
beginning or end of a transfer the number may be less).
• 000=1 Dword
• 001=2 Dword
• 010=4 Dword
• 011=8 Dword
• 100=16 Dword
• 101, 110, 111=Reserved
Reset value: Undefined.
R
Read only as 0.
DMA Channel n DAC Address—Offset 94h/B4h
The DMA channel n DAC Address register (n = 1 or 2) holds the upper 32 bits of the 64-bit PCI
address. If this register has a value of zero, the PCI address is in the low 4GB of PCI memory space
and DAC cycles are not performed on the PCI. If the value is nonzero, then DAC cycles are
performed.
This register can be written by software prior to enabling the channel, or from the fourth Dword of
the first descriptor (if the first descriptor is fetched from memory). As each subsequent descriptor is
fetched from memory, this register is either left unmodified or written from the fourth Dword of the
descriptor. In both cases, the decision whether to update this register from the descriptor is
determined by a bit in the third Dword of the descriptor. See Section 6.2.1 for more information
about DMA channel operation.
21285 Core Logic for SA-110 Datasheet
7-25