82562EP Datasheet, PDF (8/24 Pages) Intel Corporation – 82562EP 10/100 Mbps Platform LAN Connect (PLC)

82562EP — Networking Silicon
2.2
Hardware Configuration
Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test
Execute (ISOL_TEX), define the general operation of the device. Table 1 shows the pin settings for
the different modes of operation.
Table 1. 82562EP Hardware Configuration
Mode of Operation TESTEN ISOL_TCK
Normal Operating
Mode
0
0
Isolate Mode
0
1
(Tri-State and Full
Power-Down Mode)
1
1
XOR Tree
1
0
ISOL_TI
0
1
1
0
ISOL_TEX
Comments
The ISOL_TCK, ISOL_TI, and
0
ISOL_TEX pins can remain
floating.
1
The device is in tri-state and
power-down mode.
1
The device is in tri-state and
power-down mode.
0
The XOR tree is used for board
testing and tri-state mode.
NOTE: Combinations not shown in Table 1 are reserved and should not be used.
4
Datasheet