82562EP Datasheet, PDF (7/24 Pages) Intel Corporation – 82562EP 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562EP
2.0
82562EP Architectural Overview
The 82562EP is a highly integrated Platform LAN Connect device that combines 10BASE-T and
100BASE-TX physical layer interfaces. The 82562EP supports a single interface fully compliant
with the IEEE 802.3 standard. Figure 1 shows a block diagram of the 82562EP architecture.
RDN/RDP
TDN/TDP
Digital
Equalizer
Adaptation
Equalizer &
BLW correction
Digital Clock
Recovery (100)
CRS/Link 10
Detection
Digital Clock
Recovery (10)
Transmit DAC
10/100
Bias & Band-
Gap Voltage
Circuit
Clock
Generator
100Base-TX
PCS
10Base-T
PCS
Auto-
Negotiation
Control
Registers
Port LED
Drivers
LILED#
ACTLED#
SPDLED#
LAN
Connect
Interface
LAN_RSTSYNC
LAN_TXD[2:0]
3
3
LAN_RXD[2:0]
LAN_CLK
X1
Crystal
X2
25 MHz
Figure 1. 82562EP PLC Block Diagram
2.1
LAN Connect Interface
The 82562EP supports a LAN Connect Interface (LCI) as specified in the LCI Specification. The
LAN Connect is the I/O Control Hub 2 (ICH2) interface to the 82562EP. The LCI uses an 8-pin
interface, which reduces the pin count from 15, for an Media Independent Interface (MII) PHY. In
addition, its signaling protocol provides greater functionality, such as dynamic power reduction,
from a PLC in comparison to a standard MII PHY.
Figure 2 shows how the 82562EP can be used in a 10/100 Mbps ICHx design.
I_I/_/O_O C_Coo_nn_tt_rr_oo_l l_HH_ubub₄
LA(NICCH4o)nLtrAoNller
Controller
82562EZ
(P₈la₂t₅fo₆rm_2EL_PAN
C_Pon_Ln_Cect
Device)
Transmit Differential Pair
(TDP/TDN)
Receive Differential Pair
(RDP/RDN)
System Bus Interface
Magnetics
Figure 2. 82562EP PLC 10/100 Mbps Ethernet Solution
Datasheet
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