80C52 Datasheet, PDF(6/23 Page) Intel Corporation – CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

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80C52 Datasheet, PDF (6/23 Pages) Intel Corporation – CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

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8XC52 54 58

Mode

Idle

Power Down

Table 2 Status of the External Pins during Idle and Power Down

Program

Memory

ALE

PSEN

PORT0

PORT1

PORT2

Internal

Data

External

Float

Data

Address

Internal

Data

External

Float

Data

PORT3

Data

POWER DOWN MODE

To save even more power a Power Down mode can

be invoked by software In this mode the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is terminated

On the 8XC5X either a hardware reset or an external

interrupt can cause an exit from Power Down Reset

redefines all the SFRs but does not change the on-

chip RAM An external interrupt allows both the

SFRs and on-chip RAM to retain their values

To properly terminate Power Down the reset or ex-

ternal interrupt should not be executed before VCC is

restored to its normal operating level and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms)

With an external interrupt INT0 and INT1 must be

enabled and configured as level-sensitive Holding

the pin low restarts the oscillator but bringing the pin

back high completes the exit Once the interrupt is

serviced the next instruction to be executed after

RETI will be the one following the instruction that put

the device into Power Down

DESIGN CONSIDERATION

The window on the D87C5X must be covered by

an opaque label Otherwise the DC and AC char-

acteristics may not be met and the device may

be functionally impaired

When the idle mode is terminated by a hardware

reset the device normally resumes program exe-

cution from where it left off up to two machine

cycles before the internal reset algorithm takes

control On-chip hardware inhibits access to inter-

nal RAM in this event but access to the port pins

is not inhibited To eliminate the possibility of an

unexpected write when Idle is terminated by re-

set the instruction following the one that invokes

Idle should not be one that writes to a port pin or

to external memory

ONCE MODE

The ONCE (ââOn-Circuit Emulationââ) Mode facilitates

testing and debugging of systems using the 8XC5X

without the 8XC5X having to be removed from the

circuit The ONCE Mode is invoked by

1) Pull ALE low while the device is in reset and

PSEN is high

2) Hold ALE low as RST is deactivated

While the device is in ONCE Mode the Port 0 pins

float and the other port pins and ALE and PSEN are

weakly pulled high The oscillator circuit remains ac-

tive While the 8XC5X is in this mode an emulator or

test CPU can be used to drive the circuit Normal

operation is restored when a normal reset is applied

NOTE

For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors

Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded Applications Handbook Order No

270648) ââDesigning with the 80C51BH ââ

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