21150 Datasheet, PDF (56/164 Pages) Intel Corporation – PCI-to-PCI Bridge

21150
4.8.2
If the 21150 is delivering posted write data when it terminates the transaction because the master
latency timer expires, it initiates another transaction to deliver the remaining write data. The
address of the transaction is updated to reflect the address of the current Dword to be delivered.
If the 21150 is prefetching read data when it terminates the transaction because the master latency
timer expires, it does not repeat the transaction to obtain more data.
Master Abort Received by the 21150
If the 21150 initiates a transaction on the target bus and does not detect DEVSEL# returned by the
target within five clock cycles of the 21150’s assertion of FRAME#, the 21150 terminates the
transaction with a master abort. The 21150 sets the received master abort bit in the status register
corresponding to the target bus.
For delayed read and write transactions, when the master abort mode bit in the bridge control
register is 0, the 21150returns TRDY# on the initiator bus and, for read transactions, returns
FFFF FFFFh as data.
When the master abort mode bit is 1, the 21150 returns target abort on the initiator bus. The 21150
also sets the signaled target abort bit in the register corresponding to the initiator bus.
Figure 13 shows a delayed write transaction that is terminated with a master abort.
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Preliminary Datasheet