21150 Datasheet, PDF (1/164 Pages) Intel Corporation – PCI-to-PCI Bridge

21150 PCI-to-PCI Bridge
Product Features
Preliminary Datasheet
s Complies fully with the PCI Local Bus
Specification, Revision 2.1
s Complies fully with the Advanced
Configuration Power Interface (ACPI)
Specification
s Complies fully with the PCI Power
Management Specification, Revision 1.0¹
s Complies fully with Revision 1.0 of the
PCI-to-PCI Bridge Architecture
Specification
s Implements delayed transactions for all PCI
configuration, I/O, and memory read
commands—up to three transactions
simultaneously in each direction
s Allows 88 bytes of buffering (data and
address) for posted memory write
commands in each direction—up to five
posted write transactions simultaneously in
each direction
s Allows 72 bytes of read data buffering in
each direction
s Provides concurrent primary and secondary
bus operation, to isolate traffic
s Provides 10 secondary clock outputs with
the following features:
— Low skew permits direct drive of option
slots
— Individual clock disables, capable of
automatic configuration during reset
s Provides arbitration support for nine
secondary bus devices:
— A programmable 2-level arbiter
— Hardware disable control, to permit use
of an external arbiter
s Provides a 4-pin general-purpose I/O
interface, accessible through device-
specific configuration space
s Provides enhanced address decoding:
— A 32-bit I/O address range
— A 32-bit memory-mapped I/O address
range
— A 64-bit prefetchable memory address
range
— ISA-aware mode for legacy support in
the first 64KB of I/O address range
— VGA addressing and VGA palette
snooping support
s Includes live insertion support
s Supports PCI transaction forwarding for the
following commands:
— All I/O and memory commands
— Type 1 to Type 1 configuration
commands
— Type 1 to Type 0 configuration
commands (downstream only)
— All Type 1 to special cycle
configuration commands
s Includes downstream lock support
s Supports both 5-V and 3.3-V signaling
environments
s Available in both 33 MHz and 66 MHz
versions
s Provides an IEEE standard 1149.1 JTAG
interface.
1._{For 21150-AB and later revisions only. The 21150-AA does not implement this feature.}
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 278106-002
July 1998