21150 Datasheet, PDF (129/164 Pages) Intel Corporation – PCI-to-PCI Bridge

21150
Dword Bit
Name
R/W
21
Master abort mode
R/W
22
Secondary bus reset
R/W
23
Fast back-to-back enable
24
Primary master timeout R/W
Description
Controls the 21150’s behavior when a master
abort termination occurs in response to a
transaction initiated by the 21150 on either the
primary or secondary PCI interface.
When 0—The 21150 asserts TRDY# on the
initiator bus for delayed transactions, and
FFFF FFFFh for read transactions. For posted
write transactions, p_serr_l is not asserted.
When 1—The 21150 returns a target abort on
the initiator bus for delayed transactions. For
posted write transactions, the 21150 asserts
p_serr_l if the SERR# enable bit is set in the
command register.
Reset value: 0.
Controls s_rst_l on the secondary interface.
When 0—The 21150 deasserts s_rst_l.
When 1—The 21150 asserts s_rst_l. When
s_rst_l is asserted, the data buffers and the
secondary interface are initialized back to reset
conditions. The primary interface and
configuration registers are not affected by the
assertion of s_rst_l.
Reset value: 0.
Controls the ability of the 21150 to generate
fast back-to-back transactions on the
secondary interface.
When 0—The 21150 does not generate fast
back-to-back transactions on the secondary
PCI bus.
When 1—The 21150 is enabled to generate
fast back-to-back transactions on the
secondary PCI bus.
Reset value: 0.
Sets the maximum number of PCI clock cycles
that the 21150 waits for an initiator on the
primary bus to repeat a delayed transaction
request. The counter starts once the delayed
transaction completion is at the head of the
queue. If the master has not repeated the
transaction at least once before the counter
expires, the 21150 discards the transaction
from its queues.
When 0—The primary master timeout value is
2¹⁵ PCI clock cycles, or 0.983 ms for a 33-MHz
bus.
When 1—The value is 2¹⁰ PCI clock cycles, or
30.7 µs for a 33-MHz bus.
Reset value: 0.
Preliminary Datasheet
121