IXP45X Datasheet, PDF (50/148 Pages) Intel Corporation – Product Line of Network Processors

Package Information
Table 12. High-Speed, Serial Interface 0 (Sheet 1 of 2)
Name
Power
on
Reset^†
Reset^†
Normal
After
Reset
Until
Software
Enables
Possible
Configur
ations
After
Software
Enables
Type^†
Description
HSS_TXFRAME0
The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to
allow an external source become synchronized with the transmitted data. Often known as a Frame
Sync signal. Configured as an input upon reset.
Z
Z
VB
VB
I/O ^{When this interface/signal is enabled and is not being used in a system design, the interface/}
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the HSS soft
fuse (refer to Expansion Bus Controller chapter of the Intel^® IXP45X and Intel^® IXP46X Product
Line of Network Processors Developer’s Manual) and is not being used in a system design, this
interface/signal is not required for any connection.
HSS_TXDATA0
Transmit data out. Open Drain output.
When this interface/signal is enabled and either used or unused in a system design, it should be
Z
Z
VOD
VOD
OD
pulled
(refer
thoigEhxpwainthsiaon1B0-uKs^ΩCorenstirsotlolerrtcohVa^Cp^Cte^{P.rWofhtehnet}I^hn^isteⁱl^n®teI^rX^fP^a4^ce5X^isa^dnⁱd^saI^bn^lt^ee^dl^®viI^aXP^th4^e6X^HSP^Sro^sd^ou^fc^tt^fL^ui^sn^ee
of
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
HSS_TXCLK0
The High-Speed Serial (HSS) transmit clock signal can be configured as an input or an output. The
clock can be a frequency ranging from 512 KHz to 8.192 MHz. Used to clock out the transmitted
Z
Z
VB
VB
I/O data. Configured as an input upon reset. Frame sync and data can be selected to be generated on
the rising or falling edge of the transmit clock. When this interface/signal is enabled and is not
being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor.
HSS_RXFRAME0
The High-Speed Serial (HSS) receive frame signal can be configured as an input or an output to
allow an external source to become synchronized with the received data. Often known as a Frame
Sync signal. Configured as an input upon reset.
Z
Z
VB
VB
I/O ^{When this interface/signal is enabled and is not being used in a system design, the interface/}
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the HSS soft
fuse (refer to Expansion Bus Controller chapter of the Intel^® IXP45X and Intel^® IXP46X Product
Line of Network Processors Developer’s Manual) and is not being used in a system design, this
interface/signal is not required for any connection.
Note: This table discusses all features supported on the Intel^® IXP45X and Intel^® IXP46X Product Line of Network Processors. For details on feature support listed by processor,
see Table 1 on page 13.
†
For a legend of the Type codes, see Table 8 on page 43.
August 2006
50
Intel^® IXP45X and Intel^® IXP46X Product Line of Network Processors Datasheet
Document Number: 306261-004US