IXP45X Datasheet, PDF (46/148 Pages) Intel Corporation – Product Line of Network Processors

Package Information
Table 10. DDR SDRAM Interface (Sheet 2 of 2)
Name
Power
on
Reset^†
Reset^†
Normal
After
Reset
Until
Software
Enables
Possible
Configur
ations
After
Software
Enables
Type^†
Description
RECEIVE ENABLE OUT must be connected to DDRI_RCVENIN_N signal of the IXP45X/IXP46X
DDRI_RCVENOUT_N
Z
1
VO
VO
O network processors and the propagation delay of the trace length must be matched to the
clock trace plus the average DQ Traces.
DDRI_RCVENIN_N
Z
VI
VI
VI
I
RECEIVE ENABLE IN provides delay information for enabling the input receivers and must be
connected to the DDRI_RCVENOUT_N signal of the IXP45X/IXP46X network processors.
DDRI_RCOMP
Tied off
to a
resistor
Tied off
to a
resistor
Tied off to Tied off to
a resistor a resistor
O
20 Ohm 1% tolerance Resistor connected to ground used for process/temperature
adjustments.
DDRI_VREF
VCCM/2 VCCM/2 VCCM/2 VCCM/2
I
DDR SDRAM Voltage Reference — is used to supply the reference voltage to the differential
inputs of the memory controller pins.
Note: This table discusses all features supported on the Intel^® IXP45X and Intel^® IXP46X Product Line of Network Processors. For details on feature support listed by processor,
see Table 1 on page 13.
†
For a legend of the Type codes, see Table 8 on page 43.
Table 11. PCI Controller (Sheet 1 of 4)
Name
Power
on
Reset^†
Reset^†
Normal
After
Reset
Until
Software
Enables
Possible
Configur
ations
After
Software
Enables
Type^†
Description
PCI_AD[31:0]
PCI Address/Data bus used to transfer address and bidirectional data to and from multiple PCI
devices.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
Z
Z
VB
VB
I/O should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel^® IXP45X and Intel^® IXP46X Product Line of
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI Command/Byte Enables is used as a command word during PCI address cycles and as byte
enables for data cycles.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
PCI_CBE_N[3:0]
Z
Z
VB
VB
I/O _{should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse}
(refer to Expansion Bus Controller chapter of the Intel^® IXP45X and Intel^® IXP46X Product Line of
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
Note: This table discusses all features supported on the Intel^® IXP45X and Intel^® IXP46X Product Line of Network Processors. For details on feature support listed by processor,
see Table 1 on page 13.
†
For a legend of the Type codes, see Table 8 on page 43.
August 2006
46
Intel^® IXP45X and Intel^® IXP46X Product Line of Network Processors Datasheet
Document Number: 306261-004US