319537-003US Datasheet, PDF (409/450 Pages) Intel Corporation – Intel System Controller Hub

ACPI Functions
18.7.2.5
CGTNE—Core Well GPIO Trigger Negative Edge Enable Register
Offset:
Default Value:
10–13h
00000000h
Attribute:
Size:
RO, R/W
32 bits
18.7.2.6
Bit
31:10
9:0
Default
and
Access
0s
RO
0s
R/W
Description
Reserved
Trigger Enable (TE)
1 = corresponding GPIO, if enabled as input using CGIO.IO[n], will case
an SMI#/SCI when a 1-to-0 transition occurs.
0 = GPIO is not enabled to trigger an SMI#/SCI on a 1-to-0 transition.
This bit has no meaning if CGIO.IO[n] is cleared (i.e., programmed for
output)
CGGPE—Core Well GPIO GPE Enable Register
Offset:
Default Value:
14–17h
00000000h
Attribute:
Size:
RO, R/W
32 bits
18.7.2.7
Bit
31:10
9:0
Default
and
Access
0s
RO
0s
R/W
Description
Reserved
Enable (EN): When set, when CGTS.TS[n] is set, the ACPI GPE0E.GPIO
bit will be set.
CGSMI—Core Well GPIO SMI Enable Register
Offset:
Default Value:
18–1Bh
00000000h
Attribute:
Size:
RO, R/W
32 bits
Bit
31:10
9:0
Default
and
Access
0s
RO
0s
R/W
Description
Reserved
Enable (EN): When set, when CGTS.TS[n] is set, the ACPI SMIE.GPIO bit
will be set.
Datasheet
409