319537-003US Datasheet, PDF (237/450 Pages) Intel Corporation – Intel System Controller Hub

EHCI Host Controller (D29:F7)
13.2.18 PWR_CNTL_STS—Power Management Control/Status
Register
Address Offset:
Default Value:
54h–55h
0000h
Attribute:
Size:
R/W, R/WC, RO
16 bits
Default
Bit
and
Access
Description
PME Status (STS)
0 = Writing a 1 to this bit will clear it and cause the internal PME to
deassert (if enabled).
15
0
R/WC
1 = This bit is set when the EHCI would normally assert the PME# signal
independent of the state of the PME_En bit.
14:13
12:9
8
7:2
1:0
00b
RO
0h
RO
0
R/W
00h
RO
00b
R/W
NOTE: This bit must be explicitly cleared by the operating system each
time the operating system is loaded.
Data Scale (DSCA): Hardwired to 00b indicating it does not support the
associated Data register.
Data Select (DSEL): Hardwired to 0000b indicating it does not support
the associated Data register.
PME Enable (EN)
0 = Disable.
1 = Enable. Enables EHCI to generate an internal PME signal when
PME_Status is 1.
NOTE: This bit must be explicitly cleared by the operating system each
time it is initially loaded.
Reserved
Power State: This 2-bit field is used both to determine the current power
state of EHCI function and to set a new power state. The definition of the
field values are:
00 = D0 state
11 = D3_HOT state
If software attempts to write a value of 10b or 01b in to this field, the write
operation must complete normally; however, the data is discarded and no
state change occurs. When in the D3_HOT state, the Intel® SCH must not
accept accesses to the EHCI memory range; but the configuration space
must still be accessible.
When software changes this value from the D3_HOT state to the D0 state, an
internal warm (soft) reset is generated, and software must re-initialize the
function.
NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.
Datasheet
237