UPI-41AH Datasheet, PDF (4/20 Pages) Intel Corporation – UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER

UPI-41AH 42AH
UPI-41AH and UPI-42AH FEATURES
1 Two Data Bus Buffers one for input and one for
output This allows a much cleaner Master Slave
protocol
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2 8 Bits of Status
ST₇ ST₆ ST₅ ST₄ F₁ F₀ IBF OBF
D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
ST₄ – ST₇ are user definable status bits These
bits are defined by the ‘‘MOV STS A’’ single byte
single cycle instruction Bits 4–7 of the acccumu-
lator are moved to bits 4–7 of the status register
Bits 0–3 of the status register are not affected
MOV STS A Op Code 90H
1 001000 0
D₇
D₀
3 RD and WR are edge triggered IBF OBF F₁ and
INT change internally after the trailing edge of RD
or WR
During the time that the host CPU is reading the
status register the UPI is prevented from updat-
ing this register or is ‘locked out ’
4 P₂₄ and P₂₅ are port pins or Buffer Flag pins
which can be used to interrupt a master proces-
sor These pins default to port pins on Reset
If the ‘‘EN FLAGS’’ instruction has been execut-
ed P₂₄ becomes the OBF (Output Buffer Full) pin
A ‘‘1’’ written to P₂₄ enables the OBF pin (the pin
outputs the OBF Status Bit) A ‘‘0’’ written to P₂₄
disables the OBF pin (the pin remains low) This
pin can be used to indicate that valid data is avail-
able from the UPI (in Output Data Bus Buffer)
If ‘‘EN FLAGS’’ has been executed P₂₅ becomes
the IBF (Input Buffer Full) pin A ‘‘1’’ written to P₂₅
enables the IBF pin (the pin outputs the inverse of
the IBF Status Bit A ‘‘0’’ written to P₂₅ disables
the IBF pin (the pin remains low) This pin can be
used to indicate that the UPI is ready for data
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Data Bus Buffer Interrupt Capability
EN FLAGS Op Code 0F5H
1 111010 1
D₇
D₀
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4