UPI-41AH Datasheet, PDF (3/20 Pages) Intel Corporation – UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER

UPI-41AH 42AH
Table 1 Pin Description
DIP PLCC
Symbol Pin Pin Type
No No
Name and Function
TEST 0 1
2
I TEST INPUTS Input pins which can be directly tested using conditional branch
TEST 1 39 43
instructions
FREQUENCY REFERENCE TEST 1 (T₁) also functions as the event timer input (under
software control) TEST 0 (T₀) is used during PROM programming and ROM EPROM
verification It is also used during Sync Mode to reset the instruction state to S1 and
synchronize the internal clock to PH1 See the Sync Mode Section
XTAL 1 2
3
I INPUTS Inputs for a crystal LC or an external timing signal to determine the internal
XTAL 2 3
4
oscillator frequency
RESET 4
5
I RESET Input used to reset status flip-flops and to set the program counter to zero
RESET is also used during EPROM programming and verification
SS
5
6
I SINGLE STEP Single step input used in conjunction with the SYNC output to step the
program through each instruction (EPROM) This should be tied to a5V when not used
This pin is also used to put the device in Sync Mode by applying 12 5V to it
CS
6
7
I CHIP SELECT Chip select input used to select one UPI microcomputer out of several
connected to a common data bus
EA
7
8
I EXTERNAL ACCESS External access input which allows emulation testing and
ROM EPROM verification This pin should be tied low if unused
RD
8
9
I READ I O read input which enables the master CPU to read data and status words from
the OUTPUT DATA BUS BUFFER or status register
A₀
9
10
I COMMAND DATA SELECT Address Input used by the master processor to indicate
whether byte transfer is data (A₀ e 0 F1 is reset) or command (A₀ e 1 F1 is set) A₀ e 0
during program and verify operations
WR
10
11
I WRITE I O write input which enables the master CPU to write data and command words
to the UPI INPUT DATA BUS BUFFER
SYNC
11 13 O OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can
be used as a strobe for external circuitry it is also used to synchronize single step
operation
D₀ – D₇ 12 – 19 14 – 21 I O DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI
(BUS)
microcomputer to an 8-bit master system data bus
P₁₀ – P₁₇ 27 – 34 30 – 33 I O PORT 1 8-bit PORT 1 quasi-bidirectional I O lines P₁₀ – P₁₇ access the signature row
35– 38
and security bit
P₂₀ – P₂₇ 21 – 24 24 – 27 I O PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits (P₂₀ – P₂₃) interface
35 – 38 39– 42
directly to the 8243 I O expander device and contain address and data information during
PORT 4 – 7 access The upper 4 bits (P₂₄ – P₂₇) can be programmed to provide interrupt
Request and DMA Handshake capability Software control can configure P₂₄ as Output
Buffer Full (OBF) interrupt P₂₅ as Input Buffer Full (IBF) interrupt P₂₆ as DMA Request
(DRQ) and P₂₇ as DMA ACKnowledge (DACK)
PROG
25
28 I O PROGRAM Multifunction pin used as the program pulse input during PROM programming
During I O expander access the PROG pin acts as an address data strobe to the 8243
This pin should be tied high if unused
V_CC
40 44
V_DD
26 29
POWER a5V main power supply pin
POWER a5V during normal operation a12 5V during programming operation Low
power standby supply pin
V_SS
20 22
GROUND Circuit ground potential
3