SA-1110 Datasheet, PDF (4/10 Pages) Intel Corporation – Intel-R StrongARM SA-1110 Microprocessor

SA-1110
The reset controller manages the various reset sources within the SA-1110 and provides the ability
to invoke a software reset. In addition, the reset controller tracks the cause of the last known reset,
whether a hard reset, soft reset, watchdog timer expiration, or sleep mode reset.
The SA-1110 provides 28 general-purpose I/O pins, which may be programmed to generate
interrupts on rising, falling, or both edges. The user is given the option of utilizing a subset of the
GPIO pins to support extra functionality in either the serial channels or the LCD controller but may
choose to use some, all, or none of the added functionality.
Power-Management Functions
Power management provides three modes of operation: normal, idle, and sleep. In normal mode,
the CPU and peripherals are fully powered, but receive active clocks only when in use. In idle
mode, clocks to the CPU are stopped, but the clocks to the peripheral functions are active. Power
dissipation during idle mode is strongly dependent on the details of the system design. The
SA-1110 returns to normal mode from idle mode upon receipt of any enabled interrupt, including
interrupts resulting from timers expiring.
In sleep mode, once DRAM is placed in self-refresh, all functions are disabled except for the real-
time clock. Wake-up from sleep occurs upon a preprogrammed interrupt and takes 10 ms if the
3.686-MHz clock is enabled or 160 ms if the 3.686-MHz clock is disabled.
Intel^® StrongARM SA-1110 Memory and PCMCIA Control Module
The memory and PCMCIA control module (MPCM) supports four banks of fast-page-mode (FPM),
extended-data-out (EDO), and/or synchronous DRAM (SDRAM). It also supports up to six banks of
static memory; all six banks allow ROM or Flash memory, each with non-burst or burst read timings.
Additionally, the lower three static banks support SRAM, the upper three static banks support variable
latency I/O devices (with the variable data latency controlled by a shared data ready input), and the
lower four static banks support synchronous mask ROM (SMROM). SMROM is supported only on
32-bit data busses. All other dynamic and static memory types and variable latency I/O devices are
supported on either 16-bit or 32-bit data busses. Expansion devices are supported through PCMCIA
control signals that share the memory bus data and address lines to complete the card interface. Some
external glue logic (buffers and transceivers) is necessary to implement the interface. Control is
provided to permit two card slots with hot-swap capability.
Intel^® StrongARM SA-1110 Peripheral Control Module
The SA-1110 contains a six-channel DMA controller to support the high-speed data movement
inherent in serial communications. Note that the LCD controller contains its own independent
DMA channels, and that the six DMA channels are available for use by the other peripheral I/O
functions. The DMA controller is dedicated to data movement between the serial channels and
external memory, whether DRAM, SRAM, Flash, or ROM.
The LCD controller on the SA-1110 supports up to 256 colors and 16 gray-scale levels, on a single
or split-screen display with resolution up to 1024 X 1024. The LCD controller is implemented
using a patented dithering algorithm controlling the intensity of the information displayed. In the
case of color, the dithering algorithm controls which 256 of the 4096 available colors are displayed
during any given frame. Frame buffer data is used by the LCD controller as an address value,
which is then decoded as an index into a 256-entry by 12-bit wide palette RAM. If 12-bit data is
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SA-1110 Brief Datasheet