FW82801DBM-SL6DN Datasheet, PDF (362/615 Pages) Intel Corporation – Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)

LPC Interface Bridge Registers (D31:F0)
9.8.1.1
GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0)
Offset Address: A0h
Default Value:
00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, RO, R/WO, R/WC
16 bit
ACPI, Legacy
Core
Bit
15:12
11
10
9
8
7
6
5
4
3
2
1:0
Description
Global Standby Timer Timeout Count (GST_TIMEOUT) — R/W. This field sets the number of
clock ticks that the Global Standby Timer will count before generating a wake event. The GST
starts counting when the ICH4 enters the S1-M state. If a value of 0h is entered into this field the
GST will not count, and no wake event will be generated. The GST_TICK bit sets the tick rate.
Global Standby Timer Tick Rate (GST_TICK) — R/W.
0 = Counts by 65.536 seconds (1.0921 minute). This yields a GST timeout range of 1 to 17.476
1 = Counts by 2097.152 seconds (34.952 minutes). This yields a GST timeout range of
0.58 hours to 8 hours 45 minutes 22.816 seconds.
Reserved
PWRBTN_LVL — RO. This read-only bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
Deeper Sleep in S1-M state (DPRSLP_S1) — R/W. If this bit is set, then when entering the S1-M
state, the ICH4 will use the C4 sequence (rather than the standard sequence).
Enter C4 When C3 Invoked (C4onC3_EN). If this bit is set, then when software does a LVL3
read, the ICH4 will transition to the C4 state.
64_EN. Software sets this bit to indicate that the processor is an IA_64 processor, not an IA_32
processor.This may be used in various state machines where there are behavioral differences.
CPU SLP# Enable (CPUSLP_EN) — R/W.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the C3 and C4 states. This reduces the CPU
power.
Note that CPUSLP# will go active during Intel^® SpeedStep™ technology transitions and on entry
to S1-M, S3, S4 and S5 even if this bit is not set.
SMI_LOCK — R/W-Once. When this bit is set, writes to the GLB_SMI_EN bit will have no effect.
Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (i.e., once set, this
bit can only be cleared by PCIRST#).
Intel SpeedStep Enable (SS_EN) — R/W.
0 = Intel SpeedStep technology logic is disabled and the SS_CNT and SS_CNFregister will not
be visible (reads to SS_CNT will return 00h and writes will have no effect).
1 = Intel SpeedStep technology logic is enabled.
PCI CLKRUN# Enable (CLKRUN_EN) — R/W.
0 = Disable. ICH4 will drive the CLKRUN# signal low.
1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and STP_PCI#
signals.
Note that when the SLP_EN# bit is set, the ICH4 will drive the CLKRUN# signal low regardless of
the state of the CLKRUN_EN bit. This ensures that the PCI and LPC clocks will continue running
during a transition to a sleep state.
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the rate the
periodic SMI# is generated.
00 = 1 minute
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
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Intel^® 82801DBM ICH4-M Datasheet