FW82801DBM-SL6DN Datasheet, PDF (150/615 Pages) Intel Corporation – Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)

Functional Description
5.12.6.6
5.12.7
5.12.7.1
LPC Devices and CLKRUN#
If an LPC device (of any type) needs the 33-MHz PCI clock (e.g., for LPC DMA or LPC serial
interrupt), then it can assert CLKRUN#. Note that LPC devices running DMA or bus master cycles
do not need to assert CLKRUN#, since the ICH4 asserts it on their behalf.
The LDRQ# inputs are ignored by the ICH4 when the PCI clock is stopped to the LPC devices to
avoid misinterpreting the request. The ICH4 assumes that only one more rising PCI clock edge
occurs at the LPC device after the assertion of STP_PCI#. Upon deassertion of STP_PCI#, the
ICH4 assumes that the LPC device receives its first clock rising edge corresponding to the ICH4’s
second PCI clock rising edge after the deassertion.
Sleep States
Sleep State Overview
The ICH4 directly supports different sleep states (S1-M–S5), which are entered by setting the
SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several
assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the
processor can only perform one register access at a time. A request to Sleep always has higher
priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note
that thermal throttling cannot be disabled, but setting the SLP_EN bit disables thermal
throttling (since S1-M–S5 sleep state has higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state indicates a
complete loss of power.
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Intel^® 82801DBM ICH4-M Datasheet