FW82801DBM-SL6DN Datasheet, PDF (272/615 Pages) Intel Corporation – Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)

LAN Controller Registers (B1:D8:F0)
7.1.15
7.1.16
7.1.17
7.1.18
CAP_PTR — Capabilities Pointer
(LAN Controller—B1:D8:F0)
Offset Address: 34h
Default Value:
DCh
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Capabilities Pointer (CAP_PTR) — RO. Hardwired to DCh; indicates the offset within
configuration space for the location of the Power Management registers.
INT_LN — Interrupt Line Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Ch
Default Value:
00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN) — R/W. Identifies the system interrupt line to which the LAN Controller’s
PCI interrupt request pin (as defined in the Interrupt Pin Register) is routed.
INT_PN — Interrupt Pin Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Dh
Default Value:
01h
Attribute:
Size:
RO
8 bits
Bit
Description
Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN Controller’s interrupt
7:0
request is connected to PIRQA#. However, in the ICH4 implementation, when the LAN Controller
interrupt is generated PIRQ[E]# will go active, not PIRQ[A]#. Note that if the PIRQ[E]# signal is
used as a GPIO, the external visibility will be lost (though PIRQ[E]# will still go active internally).
MIN_GNT — Minimum Grant Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Eh
Default Value:
08h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in increments of 0.25 s)
that the LAN Controller needs to retain ownership of the PCI bus when it initiates a transaction.
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Intel^® 82801DBM ICH4-M Datasheet