317607-001 Datasheet, PDF (279/351 Pages) Intel Corporation – Express Chipset

Manageability Engine (ME) Registers (D3:F0)
9.1.19
MID—Message Signaled Interrupt Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
8C–8Dh
0005h
RO
16 bits
Bit
15:8
7:0
Access &
Default
RO
00h
RO
05h
Description
Next Pointer (NEXT): This field indicates the next item in the list. This
can be other capability pointers (such as PCI-Express) or it can be the
last item in the list.
Capability ID (CID): Capabilities ID indicates MSI.
9.1.20
MC—Message Signaled Interrupt Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
8E–8Fh
0080h
RO, R/W
16 bits
Bit
15:8
7
6:4
3:1
0
Access &
Default
RO
00h
RO
1b
RO
000b
RO
000b
R/W
0b
Description
Reserved
64 Bit Address Capable (C64): This bit indicates whether capable of
generating 64-bit messages.
Multiple Message Enable (MME): Not implemented, hardwired to 0.
Multiple Message Capable (MMC): Not implemented, hardwired to
0.
MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt
pins are not used to generate interrupts.
0 = Disable
1 = Enable
Datasheet
279