317607-001 Datasheet, PDF (111/351 Pages) Intel Corporation – Express Chipset

DRAM Controller Registers (D0:F0)
5.1.37
SMICMD—SMI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
CC–CDh
0000h
RO, RW
16 bits
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
Bit
15:12
11
10:0
Access &
Default
RO
0h
RW
0b
RO
0s
Description
Reserved
SMI on GMCH Thermal Sensor Trip (TSTSMI):
1 = A SMI DMI special cycle is generated by GMCH when the thermal
sensor trip requires an SMI. A thermal sensor trip point cannot
generate more than one special cycle.
0 = Reporting of this condition via SMI messaging is disabled.
Reserved
5.1.38
SKPD—Scratchpad Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
DC–DFh
00000000h
RW
32 bits
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
Bit
31:0
Access &
Default
Description
RW
Scratchpad Data (SKPD): 1 DWord of data storage.
00000000h
Datasheet
111