317607-001 Datasheet, PDF (243/351 Pages) Intel Corporation – Express Chipset

Integrated Graphics Device Registers (D2:F0,F1)
8.1.31
GDRST—Graphics Debug Reset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
C0h
00h
RO, RW
8 bits
Bit
Access &
Default
Description
7:2
RO
Reserved
0h
1
RO
Graphics Reset Status (GRS):
0b
0 = Graphics subsystem not in Reset.
1 = Graphics Subsystem in Reset as a result of Graphics Reset.
This bit gets is set to a 1 when Graphics debug reset bit is set to a 1
and the Graphics hardware has completed the debug reset sequence
and all Graphics assets are in reset. This bit is cleared when Graphics
Reset bit is set to a 0.
0
RW
Graphics Reset Enable (GR):
0b
1 = Assert display and render domain reset
0 = De-assert display and render domain reset
Render and Display clock domain resets should be asserted for at least
20 us. Once this bit is set to a 1, all graphics core MMIO registers are
returned to power on default state. All Ring buffer pointers are reset,
command stream fetches are dropped and ongoing render pipeline
processing is halted, state machines and State Variables returned to
power on default state, Display and overlay engines are halted
(garbage on screen). VGA memory is not available, Store DWORDs
and interrupts are not ensured to be completed. Device 2 I/O registers
are not available.
Device 2 Configuration registers continue to be available while
Graphics debug reset is asserted.
Datasheet
243