80960SA Datasheet, PDF (22/39 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS

80960SA
Table 8. 80960SA AC Characteristics (20 MHz)
Symbol
Parameter
Min Max Units
Notes
Input Clock
T₁
Processor Clock Period (CLK2)
25
125
ns V_IN = 1.5V
T₂
Processor Clock Low Time (CLK2) 6
ns V_T = 10% Point
= V_CL + (V_CH – V_CL) x 0.1
T₃
Processor Clock High Time (CLK2) 6
ns V_T = 90% Point
= V_CL + (V_CH – V_CL) x 0.9
T₄
Processor Clock Fall Time (CLK2)
10
ns V_T = 90% to 10% Point (1)
T₅
Processor Clock Rise Time (CLK2)
10
ns V_T = 10% to 90% Point (1)
Synchronous Outputs
T₆
Output Valid Delay
T_6AS
AS Output Valid Delay
T₇
ALE Width
T₈
ALE Output Valid Delay
T₉
Output Float Delay
Synchronous Inputs
2
20
2
20
T₁ - 11
2
18
2
17
ns
ns
ns
ns
ns (2)
T₁₀
Input Setup 1
7
ns
T₁₁
Input Hold
2
ns
T₁₂
Input Setup 2
13
ns
T₁₃
Setup to ALE Inactive
10
ns
T₁₄
Hold after ALE Inactive
8
ns
T₁₅
RESET Hold
3
ns (3)
T₁₆
RESET Setup
5
ns (3)
T₁₇
RESET Width
1025
ns 41 CLK2 Periods Minimum
NOTES:
1. Processor clock (CLK2) rise time and fall time are not tested.
2. A float condition occurs when the maximum output current becomes less than I_LO. Float delay is not tested, but should be
no longer than the valid delay.
3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-
chronous reset, synchronizing the clock can be accomplished by using AS.
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