LXT9785 Datasheet, PDF (205/226 Pages) Intel Corporation – Advanced 8-Port 10/100 Mbps PHY Transceivers

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 91. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
Bit Name
Description
Type¹ Default²
Next Page
15
(NP)
0 = Link partner has no additional next pages to send
1 = Link partner has additional next pages to send
R
0
0 = Link partner has not received Link Code Word from
Acknowledge
14
(ACK)
the LXT9785/LXT9785E
1 = Link partner has received Link Code Word from the
R
0
LXT9785/LXT9785E
Message Page
13
(MP)
0 = Page sent by the link partner is an unformatted page
1 = Page sent by the link partner is a message page
R
0
Acknowledge 2
12
(ACK2)
0 = Link partner cannot comply with the message
1 = Link partner complies with the message
R
0
Toggle
11
(T)
0 = Previous value of the transmitted Link Code Word
equalled logic one
1 = Previous value of the transmitted Link Code Word
R
0
equalled logic zero
Message/
10:0 Unformatted
Code Field
MP = 1: Code interpreted as message page
MP = 0: Code interpreted as unformatted page
R
0x000
1. R = Read Only
2. Default value at the start of auto-negotiation code word transmission.
Table 92. Port Configuration Register (Address 16, Hex 10) (Sheet 1 of 2)
Bit Name
Description
Type ¹ Default
15 Reserved
Write as 0, ignore on Read
R/W
0
0 = Normal operation
1 = Force link pass (sets appropriate registers and LEDs
to pass)
14 Link Disable
Note: Setting this bit in 100 Mbps mode by-passes the
R/W
0
descrambler lock requirement to establish link and forces
the link to the link-good state. Setting this bit produces
unreliable results if the descrambler is not locked,
13
Transmit Disable
0 = Normal operation
1 = Disable twisted-pair transmitter
R/W
0
12
Bypass Scramble 0 = Normal operation
(100BASE-TX) 1 = Bypass scrambler and descrambler
R/W
0
11 Reserved
Write as 0, ignore on Read
R/W
0
10
Jabber
(10BASE-T)
0 = Normal operation
1 = Jabber function is enabled; however, jabber status
R/W
reporting to Register bit 1.1 is disabled
0
1. R/W = Read/Write
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
the pin(s) are latched at startup or hardware reset.
3. The default value of Register bit 16.0 is determined by the G_FX/TP pin.
If G_FX/TP is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP is not tied Low, the default
value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP hardware configuration pin.
4. The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not
have a PREASEL hardware configuration pin and has a default of 0.
5. The BGA15 package does not support fiber. Default for the BGA15 package is 0.
6. NA means the bits do not have a default value and may initially contain any value.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
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