LXT9785 Datasheet, PDF (178/226 Pages) Intel Corporation – Advanced 8-Port 10/100 Mbps PHY Transceivers

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 41. Intel^® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing
REFCLK
SYNC
RxData
TPFI
t5 t6
t1
t2
t3
t4
Table 62. Intel^® LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Parameters
Parameter
Sym Min Typ¹ Max Units
Test Conditions
RxData output delay from REFCLK
rising edge
t1
1.5
–
5
ns
Minimum CL = 5 pF
Maximum CL = 20 pF
RxData Rise/Fall Time
t2
–
1
–
ns
–
Receive start of /J/ to CRS asserted
t3
–
18
26
BT²
Synchronous
sampling of SMII
Receive start of /T/ to CRS de-
asserted
t4
–
23
27
BT²
Synchronous
sampling of SMII
SYNC setup to REFCLK rising edge
t5
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge t6
1.0
–
–
ns
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
180
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003