82541ER_13 Datasheet, PDF (16/51 Pages) Intel Corporation – 82541ER Gigabit Ethernet Controller

82541ER Gigabit Ethernet Controller
3.2.5
3.2.6
3.3
10
Error Reporting Signals (2)
Symbol
SERR#
PERR#
Type
Name and Function
System Error. The System Error signal is used by the 82541ER controller to report
OD address parity errors. SERR# is open drain and is actively driven for a single PCI clock
when reporting the error.
Parity Error. The Parity Error signal is used by the 82541ER controller to report data
parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained
STS tri-state and must be driven active by the 82541ER controller two data clocks after a
data parity error is detected. The minimum duration of PERR# is one clock for each
data phase a data parity error is present.
Power Management Signals (2)
Symbol Type
Name and Function
LAN_PWR
GOOD
I
AUX_PWR I
Power Good (Power-on Reset). The Power Good signal is used to indicate that stable
power is available for the 82541ER. When the signal is low, the 82541ER holds itself in
reset state and floats all PCI signals.
Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available
and the 82541ER device should support the D3cold power state.
EEPROM and Serial FLASH Interface Signals (9)
Symbol
Type
Name and Function
EEMODE
I
EEDI
O
EEDO
I
EECS
O
EESK
O
FLSH_CE#
O
FLSH_SCK
O
FLSH_SI
O
FLSH_SO/
LAN_DISABLE#
I
EEPROM Mode. The EEPROM Mode pin is used to select the interface and
source of the EEPROM used to initialize the device. For a MIcrowire* EEPROM on
the standard EEPROM pins, tie this pin to ground with a 100 Ω pull-down resistor.
For a Serial Peripheral Interface (SPI*) EEPROM, leave this pin disconnected.
EEPROM Data Input. The EEPROM Data Input pin is used for output to the
memory device.
EEPROM Data Output. The EEPROM Data Output pin is used for input from the
memory device. The EEDO includes an internal pull-up resistor.
Note: Voltage for EEDO must be less than 0.7 V.
EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the
device.
EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the
EEPROM interface, which is approximately 1 MHz for Microwire* and 2 MHZ for
SPI.
Flash Chip Enable Output. Used to enable FLASH device.
Flash Serial Clock Output. The clock rate of the serial FLASH interface is
approximately 1 MHz.
Flash Serial Data Input. This pin is an output to the memory device.
Flash Serial Data Output / LAN Disable. This pin is an input from the Flash
memory. Alternatively, the pin can be used to disable the LAN port from a system
General Purpose Input Output (GPIO) port. It has an internal pullup device. If the
82541ER is not using Flash functionality, the pin should be connected to an
external pull-up resistor.
If this pin is used as LAN_DISABLE#, the device goes to low power state and the
LAN port is disabled when this pin is sampled low on rising edge of PCI reset.