GD82541PI Datasheet, PDF (10/46 Pages) Intel Corporation – 82541 Family of Gigabit Ethernet Controllers

82541(PI/GI/EI) — Networking Silicon
2.2
Internal MAC Architecture Block Diagram
Figure 2 shows the major internal function blocks of 82541(PI/GI/EI) MAC device. Compared to
its predecessors, the 82541(PI/GI/EI) MAC adds improved receive-packet filtering to support
SMBus-based manageability, as well as the ability to support transmit of SMBus-based
manageability packets. In addition, an ASF-compliant TCO controller is integrated into the MAC
for reduced-cost basic ASF manageability.
Host Arbiter
PCI Interface
PCI/PCI-
X Core
DMA
Engine
TX
Switch
Packet/
Manageability
Filter
Packet
ASF
Buffer Manageability
SM Bus
EEPROM Flash
Figure 2. Internal Architecture Block Diagram
TX MAC
(10/100/
1000 Mb)
RX MAC
(10/100/
1000 Mb)
RMON
Statistics
GMII/
MII
Link I/F
MDIO
MDIO
2.3
Integrated 10/100/1000Mbps PHY
The 82541(PI/GI/EI) contains an integrated 10/100/1000Mbps-capable Copper PHY. This PHY
communicates with the MAC controller using a standard GMII/MII interface internal to the
component to transfer transmit and receive data. A standard MDIO interface, accessible to
software via MAC control registers, is used to configure and monitor the PHY operation.
2.4
System Interface
82541(PI/GI/EI) provides a 32-bit PCI 2.2 bus interface which is capable of up to 66 MHz
operation in conventional PCI mode. In conventional PCI systems with a dedicated I/O bus per
connector, this interface should provide sufficient bandwidth to support a sustained 1000 Mb/sec
transfer rate. 64 KB of on-chip buffering mitigates instantaneous receive bandwidth demands and
eliminates transmit under-runs by buffering the entire outgoing packet prior to transmission.
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