IA186ES Datasheet, PDF (7/19 Pages) InnovASIC, Inc – PCI FAST ETHERNET LAN CONTROLLER

IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
NAME
serr_n
sr_ck
sr_cs
sr_di
sr_do
srl_clsn
srl_rclk
srl_rxd
srl_rxen
srl_tclk
srl_txd
srl_txen
stop_n
sym_link
sym_rxd[4]
sym_txd[4]
tck
Tdi
tdo
tms
trdy_n
Type
Description
O/D Reports errors other than parity. Signal must be valid for at least one clock
cycle. This pin pulled up by an external resistor.
O
Serial ROM clock.
O
Serial ROM chip-select pin pulled down by an internal 2 k O resistor.
O
Serial ROM data-in.
I
Serial ROM data-out pin pulled up by an internal 5 k O resistor.
I
Indicates a collision occurrence on the Ethernet cable to the IA21140AF.
Asserted and deasserted asynchronously by the external ENDEC with
respect to the receive clock.
I
Carries the recovered receive clock supplied by an external ENDEC. May be
inactive during idle periods.
I
Carries the input receive data from the external ENDEC. Incoming data
should be synchronous with receive clock (srl_rclk) signal.
I
Set when receive data is present on the Ethernet cable and cleared at the
end of a frame. Set and cleared asynchronously to the receive clock by the
external ENDEC.
I
Carries the transmit clock supplied by an external ENDEC. Must be always
active, even during reset.
O
Carries the serial output data from the IA21140AF and is synchronized to
transmit clock signal.
O
Signals an external ENDEC that the IA21140AF transmit is in progress.
I/O The current target is requesting the bus master to stop the current
transaction.
O
Descrambler is locked to the input data signal.
I
This signal and the four receive lines mii_sym_rxd[3:0], provide five parallel
data lines in symbol form for use in PCS mode. Data is driven by an external
PMD device and is synchronized with respect to the mii_sym_rclk signal.
O
This signal and the four transmit lines mii_sym_txd[3:0], provide five parallel
data lines in symbol form for use in PCS mode. Data is synchronized on the
rising edge of mii_sym_tclk.
I
During JTAG test operations this clock shifts state information and test data
into and out of the IA21140AF. The pin should not be left unconnected.
I
During JTAG test operations this pin serially shifts test data and instruction
into the IA21140AF. The pin is pulled up by an internal 5 k O resistor and
should not be left unconnected.
O
During JTAG test operations this pin serially shifts test data and instructions
out of the IA21140AF.
I
Controls the state operation of JTAG testing in the IA21140AF. The pin is
pulled up by an internal 5 k O resistor and should not be left unconnected.
I/O Indicates the readiness of the target’s agent to complete the current data
phase of the transaction. During reads, this signal indicates that valid data is
present on AD lines. During writes, this signal indicates the target is ready to
accept data. A data phase is completed on any clock when both irdy_n and
trdy_n are set.
Copyright © 2001
innovASIC
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