IA186ES Datasheet, PDF (12/19 Pages) InnovASIC, Inc – PCI FAST ETHERNET LAN CONTROLLER

IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
PCI Other Signals:
Timing Diagram
clk
output
Tval (max)
Ton
Tval (min)
Toff
Vtest*
input
Th
Tsu
Note: Vtest is 1.5 V in a 5.0 V signaling environment and is
0.4 * vdd_clamp in a 3.3 V signaling environment.
Timing Characteristics
Symbol Parameter
Tval
clk-to-signal valid delay
Ton
Float-to-active delay from clk
Toff
Active -to-float delay from clk
Tsu
Input signal valid setup time before clk
Th
Input signal hold time from clk
Min Max Unit
2
11
ns
2
-
ns
-
28
ns
7
-
ns
0
-
ns
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG210010110 -00
Page 12 of 19
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