IA186ES Datasheet, PDF (6/19 Pages) InnovASIC, Inc – PCI FAST ETHERNET LAN CONTROLLER

IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
NAME
irdy_n
mii_clsn
Carrier sense
mii_crs
mii_dv
mii_err
mii_mdc
mii_mdio
mii_srl
mii_sym_rclk
mii_sym_rxd[3:0]
mii_sym_tclk
mii_sym_txd[3:0]
mii_txen
Nc
Par
pci_clk
perr_n
rcv_match
req_n
rst_n
sd
Type
Description
I/O When the IA21140AF is the bus master, this signal is asserted during write
operations indicating valid data is present on the 32-bit ad bus. It is asserted
during read operations to indicate the master is ready to accept data. It is
asserted during a write to indicate that valid data is on the AD lines. A data
phase is completed on any rising edge of the clock when both irdy_n and
trdy_n are asserted. Wait cycles are inserted until both these signals are
asserted together.
I
When an external physical layer protocol (PHY) device detects a collision, it
asserts this signal.
I
The PHY sets this bit when the media is active.
I
An external PHY sets this bit when receive data is on the mii_sym_rxd lines
and is cleared at the end of the packet. This signal is synchronized with
mii_sym_rclk.
I
When a data decoding error is detected by an external PHY device, this pin
gets set. It is synchronized to mii_sym_rclk and can be set for a minimum of
one receive clock. It sets the cyclic redundancy check (CRC) error bit in the
receive descriptor (RDES0) when it is set during a packet reception.
O
Goes to the PHY devices as timing reference for the transfer of information
on the mii_mdio signal.
I/O Transfers control information and status between the IA21140AF and PHY.
O
Set when the MII/SYM port is selected. Cleared when the SRL port is
selected.
I
This clock, recovered by the PHY, supports either the 25 MHz or 2.5 MHz
receive clock.
I
When MII mode is selected, these four parallel data lines receive data that is
driven by external PHY that attached the media. Synchronized to the
mii_sym_rclk signal.
I
This 25 MHz or 2.5 MHz transmit clock is supplied by the external physical
layer medium dependent device (PMD) and must always be active.
O
These four parallel transmit data lines are synchronized and latched by the
external PHY on the rising edge of the mii_sym_tclk signal.
O
This signal indicates a transmit to an external PHY device. It reflects the
transmit activity of the MAC sublayer when in the PCS mode (CSR6[23]).
O
No connection pins
I/O Even parity bit for the 32-bit ad bus and the 4-bit c_be_n lines. It is driven by
the master for address and write data phases and driven by the target for
read data phases.
I
Timing of the PCI related functions is based on this DC to 33 MHz clock. All
bus signals except int_n and rst_n are sampled on the rising edge of this
clock.
I/O Used for reporting data parity errors during all PCI transactions except a
special cycle.
O
Set when a received packet passes address recognition.
O
Request to the bus arbiter for the IA21140AF to use the bus.
I
When asserted for at least 10 PCI clock cycles, the IA21140AF is reset to its
initial state. PCI output pins are tristated and all PCI O/D signals are left
floating.
I
Supplied by an external PMD device.
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG210010110 -00
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