IA82510 Datasheet, PDF (6/14 Pages) InnovASIC, Inc – ASYNCHRONOUS SERIAL CONTROLLER

IA82510
ASYNCHRONOUS SERIAL CONTROLLER
DC Characteristics
Data Sheet
As of Production Ver. 01
Symbol
VIL
VIH1
VIH2
VOL
VOH
ILI
ILO
ICC
IPU
ISTBY
IOHR
IOLR
CIN
CIO
CXTAL
Parameter
Input Low Voltage
Input High Voltage-Cerdip
Input High Voltage-LCC
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Leakage Current
Power Supply Current
Strapping Pullup Resistor
Standby Supply Current
RTSn, DTRn Strapping Current
RTSn, DTRn Strapping Current
Input Capacitance
I/O Capacitance
X1, X2 Load
Notes
(1)
(1)
(2)
(2),(8)
(3),(8)
(4)
(5)
(6)
(12)
(9)
(10)
(11)
(7)
(7)
Min
Max
Unit
-0.5
0.7
V
2.1
VDD+.07
V
2.1
VDD+.07
V
0.4
V
2.4
V
±1
µA
±1
µA
1.12 mA/MHz
-283
-137
µA
100
µA
1.92
mA
N/A
mA
5
pF
6
pF
6
pF
Notes:
1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @IOL = 1.92 mA
3. @IOH = 1.92 mA
4. 0< VIN <VCC
5. 0.4V < VOUT < VCC – 0.4V
6. VDD = 5.5V, VIL = 0.7V (max), VIH = VDD – 0.7V (min), Typ. Val = 1.12 mA/MHz (Not
Tested), Ext. 1X CLK, IOL = IOH = 0
7. Freq. = 1 MHz
8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
9. Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output
drive requirements and is measured with the clocks stopped and all inputs tied to VDD or
VSS, configured to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for
logic HIGH.
11. Applies only during hardware reset for clock configuration options. Strapping current for
logic LOW.
12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V, VDD = 5.5V
Copyright © 2001
innovASIC

The End of Obsolescence™
ENG211001219-01
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