IA82510 Datasheet, PDF (13/14 Pages) InnovASIC, Inc – ASYNCHRONOUS SERIAL CONTROLLER

IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
Production Version -00, Errata
The following errata are known problems with the -00 version of the IA82510. This is inclusive of
all package types and environment grades. A workaround to the identified problem has been
provided where possible.
1. Problem: Scrambled data during boot code shuts down UART, however device works for
application code
Analysis: The RX FIFO is locked, configuration of all registers is done, then the RX FIFO is
unlocked just before entering loopback mode in both boot and application code before normal
operations begin. Boot code additionally does a blind block read of all registers before normal
operations including two reads from the unwritten RX Data FIFO. RX unlock command is
inadvertently incrementing the write pointer. For boot code, the two reads of RX data cause
the read/write pointers to be permanently out of sync. For application code, the pointers end
up synched to the same location, only because the code waits for four characters before
reading. This ends up causing an RX overrun, but to our favor because the pointers are now
synched.
Workaround: Execute a “Flush RX FIFO” command (via RCM register) after configuration
and block read is complete.
2. Problem: Device does not operate at 8 MHz in divide-by-one mode
Analysis: System testing revealed this operational deficiency.
Workaround: Switch to divide-by-two mode using 2X clock input
3. Problem: Setting CLCF to x30, which effectively generates the TX clock from the incoming
SCLK signal, kills all transmits.
Analysis: Configuration of PMD inadvertently set so RI function is selected instead of SCLK
function. Original Intel device allows SCLK through anyway, IA82510 suppresses it.
Workaround: Set correct configuration for PMD allows TX clock generation
4. Problem: Receiving streamed data has many framing errors and corrupt data when connected
to some modems.
Analysis: Shortened stop bit followed immediately by next start bit does not correctly detect
that start bit.
Workaround: Configure external modem to transmit two stop bits
5. Problem: Transmission of streamed data does not return interrupt.
Analysis: Stray read of GIR sets TX FIFO interrupt hold logic, but this logic does not reset
when GER[1] is de-asserted..
Workaround: Reset logic with write to TX data or avoid stray reads of GIR
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