IA186EB Datasheet, PDF (33/85 Pages) InnovASIC, Inc – 8-Bit/16-Bit Microcontrollers

IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Data Sheet
July 10, 2011
Table 7. IA186EB Pin/Signal Descriptions (Continued)
Signal
t1out
test_n
txd0
txd1
ucs_n
v_cc
v_ss
wr_n
Name
t1out
test_n/busy
txd0
p2.1/txd1
ucs_n
v_cc
v_ss
wr_n
Pin
PLCC LQFP
47
34
14
3
52
39
58
45
30
18
1, 23, 11, 29,
42, 64 50, 71
2, 22,
43, 63,
65, 84
5
10, 30,
49, 51,
70, 72
74
PQFP
77
46
2
8
61
13, 34,
54, 72
12, 14,
33, 35,
53, 73
37
Description
timer 1 output. Output. Depending on the
Timer Mode programmed for Timer 1, this
output can provide a single clock or a
continuous waveform.
test. Input. Active Low. When the test_n
input is high (i.e., not asserted), it causes the
IA186EB to suspend operation during the
execution of the WAIT instruction. Operation
resumes when the pin is sampled low
(asserted).
Transmit (tx) data, Serial Port 0. Output. This
pin is the serial data output for Serial Port 0.
During synchronous serial communications,
txd0 becomes the transmit clock (rxd0
functions as an output for data transmission).
Transmit (tx) data, Serial Port 1. Output. This
pin is the serial data output for Serial Port 1.
During synchronous serial communications,
txd1 becomes the transmit clock (rxd1
functions as an output for data transmission).
upper chip select. Output. Active Low. This
pin provides a chip select signal that will be
asserted (low) whenever the address of a
memory bus cycle is within the address space
programmed for that output.
Power (v_cc). This pin provides power for the
IA186EB device. It must be connected to a
+5V DC power source.
Ground (v_ss). This pin provides the digital
ground (0V) for the IA186EB. It must be
connected to a v_ss board plane.
write. Output. Active Low. When asserted
(low), wr_n indicates that data available on the
data bus are to be latched into the accessed
memory or I/O device.
IA211080314-13
UNCONTROLLED WHEN PRINTED OR COPIED
Page 33 of 85
http://www.Innovasic.com
Customer Support:
1-888-824-4184